HDMI Demo in 2019.1

[MichelleNicholes]

Yes I am aware that the demo was created in 2020.1 and it does work with 2020.1.

I am not a big fan of Vitis just yet and so I wanted to get it to work in 2019.1.

I literally created the demo in 2020.1 and then wrote the project to tcl then modified the tcl file for 2019.1 so I know the design is exactly the same.  I played around with different combinations of the libraries provided in the demo vs the master library.

First I noticed that the vivado library uses dynamic clock 1.2 but gives errors that its Zybo Z7-10 not -20

 [IP_Flow 19-4965] IP ila_pixclk was packaged with board value 'digilentinc.com:zybo-z7-10:part0:1.0'. Current project's board value is 'digilentinc.com:zybo-z7-20:part0:1.1'. Please update the project settings to match the packaged IP.

I know its the dynamic clock because when I use the dynamic clock that comes with the demo for 2020.1 the message changes to -20 1.0 which mine is -20 1.1.

I also noticed that the TC in 2020.1 is 6.2 which 2019.1 uses 6.1.   

There is another person who asked a question before about the com port not working which I get the same thing when running in 2019.1

HDMI demo not working - FPGA - Digilent Forum

I get the color pattern but the com port becomes unresponsive and it never tells me the HDMI input connects.

Now, I am leaning towards the TC being the difference given its 6.2 in 2020.1 and not 6.1 which is in 2019.1.  Not really willing to copy 2020.1 xilinx stuff over to 2019.1

I did install 2018.2 and I was able to get the 2018 version to work.

Anyways, any other ideas as to why I am not getting the same results in 2019.1  Same design and same code minus using TC 6.2 in 2020.1?

I have attached the 2019.1 tcl script with files needed in case someone wants to help figure this out.  Oh I just realized I have the script pointing to my vivado libraries so you will need to edit the script for your locations.

test.zip

Edited June 17, 2022 by MichelleNicholes
Updated info

[JColvin]

Hi @MichelleNicholes,

I apologize for the delay.

I happened to find an old HDMI demo for the Zybo Z7-20 for 2019.1 that is labeled as experimental on my computer. I will test it and if it works I will be sure to attach an exported version of the project.

Thanks,
JColvin

[JColvin]

  

Hi @MichelleNicholes

I talked to one of my co-workers who remembered having a similar issue to what you are describing (since my existing project was replicating the same issues you were describing) and they were able to help me find the bug in the Xilinx software driver that is causing the issue (this bug is fixed in later versions of SDK/Vitis).
Basically, there a bug in the xvtc_intr.c source file in the XVtc_IntrHandler function (in 2019.1) where it has a line that says

/* Spurious interrupt has happened */
	if (PendingIntr | XVTC_IXR_SPURIOUS_INTR_MASK) {
		ErrorStatus = 0;
		XVtcPtr->ErrCallBack(XVtcPtr->ErrRef, ErrorStatus);
		return;
	}

But that bitwise OR function always returns false no matter what the parameters are, so it needs to be changed to an AND, i.e.

/* Spurious interrupt has happened */
	if (PendingIntr & XVTC_IXR_SPURIOUS_INTR_MASK) {
		ErrorStatus = 0;
		XVtcPtr->ErrCallBack(XVtcPtr->ErrRef, ErrorStatus);
		return;
	}

You can permanently fix this in your 2019.1 installation by finding the file in your Vivado installation and making the change. For me, this file was in

Quote

D:\Xilinx\SDK\2019.1\data\embeddedsw\XilinxProcessorIPLib\drivers\vtc_v8_0\src\xvtc_intr.c

You can verify which numbered version of the VTC is being used by checking the BSP folder in the libsrc folder (screenshot attached oh what you will be looking for).

After you make this change in the actual Vivado installation, you should just be able to right-click on the bsp folder in SDK and choose "Re-generate BSP Sources". The project should then be able to run and capture source frames from the host computer (or at least it is working for me on my setup).

Let me know if you have any questions.

Thanks,
JColvin