I am trying to transfer the data via UART on the nexys 3 board within a loop of while but getting a error

[devchandil]

The code is as follows:

----------------------------------------------------------------------------------

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

 

entity uartwithclk is
PORT(
CLOCK_50 : in std_logic;
SW : in std_logic_vector(9 downto 0);
KEY : in std_logic_vector(3 downto 0);
UART_T : out std_logic;
CLK_OUT : inout  STD_LOGIC;
RESET : in  STD_LOGIC
);
end uartwithclk;

architecture Behavioral of uartwithclk is
SIGNAL COUNT : INTEGER:=0;
SIGNAL loop_counter : integer;
SIGNAL TEMP : STD_LOGIC:='0';
SIGNAL TX_DATA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL TX_START: STD_LOGIC:='0';
SIGNAL TX_BUSY: STD_LOGIC;
COMPONENT com
PORT(
           CLK : in  STD_LOGIC;
           START : in  STD_LOGIC;
           BUSY : out  STD_LOGIC;
           DATA : in  STD_LOGIC_VECTOR (7 downto 0);
           TX_LINE : out  STD_LOGIC
);
END COMPONENT com;
TYPE t_2KB IS ARRAY (0 TO 2047) OF std_logic_vector (7 DOWNTO 0);
SIGNAL mem : t_2KB;
begin
C1 : com PORT MAP(CLK_OUT,TX_START,TX_BUSY,TX_DATA,UART_T);
PROCESS(CLOCK_50,RESET)
VARIABLE I : integer range 0 to 2000;

BEGIN 

IF RESET='1' THEN
COUNT<=0;
TEMP<='0';
ELSIF RISING_EDGE(CLOCK_50) THEN
COUNT<=COUNT+1;
IF COUNT=1 THEN
TEMP<=NOT TEMP;
COUNT<=0;
END IF;
END IF;
CLK_OUT<=TEMP;
------------------------------------------------------- TILL HERE CLK IS DIVIDED BY 2

 I:=0;
            while(I<=5 and CLOCK_50'EVENT AND CLOCK_50='1' ) loop --error is present here "Edge or event as condition for a return, exit or next statement is not supported"

IF(CLOCK_50'EVENT AND CLOCK_50='1') THEN
IF(KEY(0)='1' AND TX_BUSY='0') THEN
TX_DATA<=SW(7 DOWNTO 0);
TX_START<='1';
ELSE
TX_START<='0';
END IF;
END IF;
I:=I+1;
END loop;

END PROCESS;
end Behavioral;

 

-----------------------------------------------------------------------------------------------------------------------------------------

The component is :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity com is
    Port ( CLK : in  STD_LOGIC;
           START : in  STD_LOGIC;
           BUSY : out  STD_LOGIC;
           DATA : in  STD_LOGIC_VECTOR (7 downto 0);
           TX_LINE : out  STD_LOGIC);
end com;

architecture Behavioral of com is
SIGNAL PRSCL: INTEGER RANGE 0 to 5208:=0;
SIGNAL INDEX: INTEGER RANGE 0 to 9:=0;
SIGNAL DATAFLL: STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL TX_FLG: STD_LOGIC:='0';
begin
PROCESS(CLK)
begin
IF(CLK'EVENT AND CLK='1') THEN
   IF(TX_FLG='0' AND START = '1') THEN
    TX_FLG<='1';
    BUSY<='1';
    DATAFLL(0)<='0';
    DATAFLL(9)<='1';
    DATAFLL(8 downto 1)<=DATA;
    END IF;
    IF(TX_FLG='1') THEN
    IF(PRSCL<5207) THEN
    PRSCL<=PRSCL+1;
    ELSE
    PRSCL<=0;
    END IF;
    IF(PRSCL=2607) THEN
    TX_LINE<=DATAFLL(INDEX);
    IF(INDEX<9)THEN
    INDEX<=INDEX+1;
    ELSE
    TX_FLG<='0';
    BUSY<='0';
    INDEX<=0;
    END IF;
    END IF;
    END IF;
    END IF;
    
    END PROCESS;

end Behavioral;
 

I am new to VHDL so any forgive me for any common or silly mistake

[hamster]

In most cases a loop can not be mapped to digital logic, so it can not be implemented within an FPGA.  

For most designs the looping is implicit in the event that triggers a process to be invoked (e.g. the ticking of a clock signal).

Try rewriting it to avoid loops completely. ...

[D@n]

While I think hamster found your immediate problem, I would also recommend you avoid the asynchronous reset.  Such resets can often have unpredictable results, particularly in large designs.

Dan

[hamster]

I tried really hard to avoid coding it for you, but here is code that has the spirit of what you need to do. I haven't tried to compile or debug it, but it should provide a framework that will guide you....

... the headers and top of the module....
   SIGNAL COUNT : INTEGER:=0;
   SIGNAL I     : integer range 0 to 2000;
BEGIN

--------------------------------------------------------------------------------------
-- I am pretty sure that this will divide the clock by four
--------------------------------------------------------------------------------------
PROCESS(CLK, RESET)
BEGIN
    IF RESET='1' THEN
        COUNT<=0;
        TEMP<='0';
    ELSIF RISING_EDGE(CLOCK_50) THEN
        COUNT<=COUNT+1;
        IF COUNT=1 THEN
            TEMP<=NOT TEMP;
            COUNT<=0;
        END IF;
    END IF;
    CLK_OUT<=TEMP;
END PROCESS;

PROCESS(CLK,RESET)
BEGIN
    IF RESET='1' THEN
        I <=0;
    ELSIF RISING_EDGE(CLOCK_50) THEN
        IF I < 5 THEN
            IF(KEY(0)='1' AND TX_BUSY='0') THEN
                TX_DATA<=SW(7 DOWNTO 0);
                TX_START<='1';
                I <= I+1;    
            ELSE
                TX_START<='0';
            END IF;
        END IF;
    END IF;
END PROCESS;

... the rest of the code....