An common17-70 error in creating binary file

[Harry671]

hi,

I saw similar errors in the website. but cannot find a definite solution to this. I am using vcu128 board. I made all in the design properly but getting this error. I have learned from the error message and the vivado videos i need to make some tcl script o make binary file. I made op level design and a wrapper for my design, added *.xdc file before make binary file. I am using vivado 2020.1. I would really appreciate if one could get back to me ASAP. I need to deliver this by next monday. no vivado document cover this error

 

Here is the exact error message below

[Common 17-70] Application Exception: Top module not set for fileset 'sources_1'. Please ensure that a valid value is provided for 'top'. The value for 'top' can be set/changed using the 'Top Module Name' field under 'Project Settings', or using the 'set_property top' Tcl command (e.g. set_property top [current_fileset]).