Harry671

hi, any one familiar with this error. it look like something wrong with vivado tool. maybe something like licensing issue. [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted: mac_i/axi_ethernet_0/inst/mac/inst/bd_1571_mac_0_core () If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation. Please reply ASAP because need to deliver something by next Tuesday. Thanks Harry

hi, I saw similar errors in the website. but cannot find a definite solution to this. I am using vcu128 board. I made all in the design properly but getting this error. I have learned from the error message and the vivado videos i need to make some tcl script o make binary file. I made op level design and a wrapper for my design, added *.xdc file before make binary file. I am using vivado 2020.1. I would really appreciate if one could get back to me ASAP. I need to deliver this by next monday. no vivado document cover this error Here is the exact error message below [Common 17-70] Application Exception: Top module not set for fileset 'sources_1'. Please ensure that a valid value is provided for 'top'. The value for 'top' can be set/changed using the 'Top Module Name' field under 'Project Settings', or using the 'set_property top' Tcl command (e.g. set_property top [current_fileset]).