NetFPGA-1G-CML + FMC

[SNGUYEN]

Hello,

I'm trying to connect Ethernet FMC 4 Port 1Gb  to a NetFPGA High pin count FMC connector (VITA 57) with 100 Select-IO and 4 GTX serial pairs on board NetFPGA-1G-CML. 

However, it failed, due to a BUFIO error with the RGMII-RX-IN DATA signals (attached image).
Anyone who has ever connected an external FMC Ethernet on this board please help.
All quick replies I am very grateful.

Thanks.

 

[elodg]

As I said in the other similar post too, this is due to clock primitives being placed in a different region than the I/O primitives it should clock. In your case, since the RGMII input pins are fixed by the FMC pinout, you have to figure out why is bufio_rgmii_rx_clk placed in a different region. You might be trying to clock I/O primitives across multiple regions, which the BUFIO cannot do.

 

[zygot]

What FMC mezzanine Ethernet board are you using? Usually, quad Ethernet FMC cards provide a clock source. Is this an HDL or IPI project? While I have no argument with the first reply to your question, I've never seen this type of error, having done a lot of DDR based interfaces. What version of the tools are you using?

I've used the UMFT601X USB 3.0 mezzanine card with the NetFPGA-1G-CML Ethernet PHYs and DDR in one design. Not sure why you need to add 4 Ethernet interfaces to a board that already has 4 of them. That's a lot of clock domains...

The NetFPGA-1G-CML has disappointing DDR3 performance and not enough clocking options for a board that's supposed to provide a platform for its intended purpose. Of course, it's also a lot cheaper than any alternative that I'm aware of. The only thing that I haven't tried to use is the QDRII+ because the schematic is just plain wrong and even though Digilent claims to test every board won't provide any support to prove it. It's also a very power hungry device for 1 or 2 MB of pseudo-DPRAM. Edited April 26, 2022 by zygot