ARTY A7- multiple VHDL Code combining in to one Vivado design...

[PeterModbury]

Hi I am using Vivado 2020.2 and trying to master combing multiple  VHDL  files  into on Vivado  Design.

Each Design has been tested and works in isolation. Each has it own XDF file driving their own  logic inputs / outputs.

One is a Pulse Processor synchronizing to a external 1O MHz CLOCK( WITH THE external  10 MHz coming in  on a I/O input pin, and various timing signals coming out on the PMODs  JA,JB JC and JD. 

The second design is a UART and some "CASTING" between Std Logic Vectors and integers. 

Each design have their own I/O, and the only shared input is the 100MHz clock. 

Now I want to combine in Vivado ONE design. I know I need  to generate the top file with the individual designs below, but the finer specifics and necessary detail is not not apparent on any of the training/ or targeted searches.  I would expect this is "102" level training . 

Can any one  point to any appropriate videos links . Any advise appreciated . 

Regards. Peter. 

[zygot]

There is plenty of Digilent IP and project source code available to help guide you with this. And hierarchical HDL is a basic level skill.

Browse the Digilent Forums, the Digilent support resources, and Xilinx resources using the Documentation Navigator for example designs. You'll find that stuff posted in the Digilent Project Vault ( if you ignore all of the stuff that should be in some other forum ) might be written in a form that is more accessible to someone learning an HDL.