DVI2RGB Reset?

[mjrx7]

I am trying to simulate the DVI2RGB IP but when I run the simulation and feed in 1010101011 (sending in LSB first) the IP shows that it is receiving 0101011101, pState in phaseAlign stays in idle mode, pBlankBegin remains 0, and pTimeoutOvf remains 0, so therefore it never tries to shift the data around to find the proper sequence of where it begins and ends.

I'm not sure if I'm handling the reset incorrectly. I am generating a 200 MHz reference clock using the clocking wizard, and I am using the locked signal out of clock wiz to bring the DVI2RGB IP out of reset (aRst). pRst I have tied to '0', resets set to active high.

 

Thanks,

Matt

[elodg]

You are driving aRst correctly from the MMCM locked output. One RefClk is stable and aRst is de-asserted, the receiver state machine needs to perform the following in sequence: clock recovery (confirm with TMDS_Clocking/aLocked), phase alignment (pAligned/pMeVld), and channel bonding (pMeRdy). It sounds like the clock has not been recovered yet and everything downstream is still in reset. Otherwise timeout would be counting if no token is detected.

[Ppspendse]

On 3/8/2022 at 4:15 PM, mjrx7 said:

I am trying to simulate the DVI2RGB IP but when I run the simulation and feed in 1010101011 (sending in LSB first) the IP shows that it is receiving 0101011101, pState in phaseAlign stays in idle mode, pBlankBegin remains 0, and pTimeoutOvf remains 0, so therefore it never tries to shift the data around to find the proper sequence of where it begins and ends.

I'm not sure if I'm handling the reset incorrectly. I am generating a 200 MHz reference clock using the clocking wizard, and I am using the locked signal out of clock wiz to bring the DVI2RGB IP out of reset (aRst). pRst I have tied to '0', resets set to active high.

 

Thanks,

Matt

Hi, I am also trying to simulate DVI2RGB IP and having a similar issue. did you find any way to work it arround?. if yes could you mind sharing solution?