I have fallen into the Xilinx SDK discontinue trap in Version Vivado 2019.2 on...

[PeterModbury]

Hi All- I have fallen into the Xilinx SDK  discontinue trap in version Vivado 2019.2. I am on a "roll with" SKD Microblaze. I  have Vivado 2020.2 that does not include SDK. If I down load Vivado 2019.1 - this is the last  operating SDK version- Can I expect  my 2020.2  VHDL to run on 2019.1 version- given my VHDL is very simple bit bashing logic lines- and no IP. I am in the process of attempting a UART but in the SDK ( part of training we paid for  ... but will be used in a lab prototype  as soon as possible ... my management expect it to be routine...). I will have to remove 2022.2 version to fit 2019.1 (last SDK?)version on my lap top.  If there  are going to be hiccups  I would like to know before.  

Alternative shall I digest.. the detailed Vitis .. 

https://projects.digilentinc.com/whitney-knitter/hello-microblaze-on-arty-a7-70d9e1

  

My immediate object is to get some parameters in to my VHDL via a Rx UART receiving integers. No doubt there are some tutorial I am not yet aware of. 

Or  the best to digest Vitis or pursue SDK in  Vivado 2019.1 version? 

 Any advice appreciated.. 

 

[zygot]

I still use Vivado 2019.1 for other reasons for a about half of my project development; this includes ZYNQ and al HDL projects for various reasons. Eventually I will have to use VIvado 2021.2 for non-Linux ZU7EV development but so far this hasn't been necessary. I have used Vivado 2021.2 for ZU7EV HW design. Still haven't done a Vivis software project.

If your design uses the MicroBlaze IP then it's unlikely that transitioning back to a previous version will not entail a bit of effort. If all you want to do is use a UART to set some register values in a logic design you don't need a soft processor. Most of my designs use either the on-board UART or a separate TTL USB UART cable to write and read registers from a PC. There are examples of Verilog and VHDL UART implementations available on the Digilent Forum. Be aware that writing binary data through a UART isn't straight-forward; but you can always send two ascii characters to represent an 8-bit hex value. Using this approach allows you to use a simple Serial Terminal application to interact with your design. Yes data transfer is half as fast but at 921600 you can't type fast enough to notice. All of my project use this method, at some point. No SDK or Vitis needed.

Since you are starting out you might just want to consider learning how to use Vitis if you must use the Xilinx soft-processor IP.

For your board, there's no compelling reason to download 40+ GB of installer data to use Vivado 2019.1. I'd go with the earliest version of Vivado that supports the device and package on my board if doing just an HDL design; you can save yourself at least 80% of the disk space and install time.

Perhaps it might be worth the cost of a really cheap ZYNQ board for you to do what you want easily. See the following link:
https://forum.digilentinc.com/topic/22512-manipulate-pl-logic-using-ps-registers/

Sometimes you want to learn a proper FPGA development flow and sometimes you just want to get to working on the stuff that interests you, Time is expensive so do the analysis. A design/development strategy that works best for me might not be one that works best for anyone else. Assess your skill level and be flexible with an approach.

Edited March 4, 2022 by zygot

[PeterModbury]

HI-  Thanks for your comments. Sorry for delay.  We have decided to go back to version 2017.3 with SDK, but as expected just plan old  VHDL will not port  back- no big deal- just need to re create and cut and paste in, and should  run ok. No explanation way - just  will not open, even  though  there is no IP- just plain VHDL. 

The main push is to get SDK running on 2017.3 and get on with the Job( if IP UART effort  is warranted…/ a benefit .)

Ironically I had to go to a faster laptop since synthesis (with IP) took hours compared to minutes on multi core- another  reason to keep it simple. 

Have a UART of sorts running. but will need to tidy up if I need it … base on..
UART in VHDL and Verilog for an FPGA (nandland.com)

https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html
 Thanks Russell  !
 
Thanks for the comments loading the older versions and taking less disk space. 

Comments greatly appreciated.
P.