Genesys ZU 3eg- hello world

[Enthusiastic]

Hi everyone,

I am working on Digilent Genesys zu-3eg zynq ultrascale+ MPSOC board. I was trying to run the basic hello world program which is provided by Digilent- https://digilent.com/reference/programmable-logic/genesys-zu/demos/hello-world?redirect=1 

In the final step of "Build a Vitis application" where we are building the master_system project, I am encountering the following error :

 

Could someone please help with the above issue. 

Thank you 

[John J]

I had the same issue, but it just went away after a few clean and build iterations while I was inspecting the configuration.  I have not had that particular problem since.

I'm using the Vivado/Vitis 2021.2 version and latest Digilent files.

I repeated the instructions mentioned above several times and added additional steps to write my own procedure for creating new projects for a specific external hardware configuration.  Oddly, I ran into different issues every time--even when I knew I had very closely duplicated the steps.

The Xilinx Vivado/Vitis tools have many project related issues that appear to manifest themselves in many ways.  Sometimes just viewing particular project properties appears to change or fix the issues, but many times it takes some serious digging.  For example, I'm developing on a Linux machine, but after using the project for a couple of weeks, it still has Windows paths in the configuration files that won't go away and are very hard to track down in Vitis.  I ended up fixing some by manually editing the project files.

 

[elodg]

The very same instructions you linked tackle this expected error in the last 4 steps of the "Build a Vitis Application" section. Did you perform those?

The background is that due to a platform build bug the boot components have been separated out from the platform and you need to provide the links to the external executables.

[Enthusiastic]

Hi,

Thank you so much for your reply. 

I have followed exactly the same steps mentioned in the above link. I have performed the last 4 steps to tackle the error message of missing fsbl.elf file that you mentioned in the reply above. 

The error I am encountering occurs when I build the master_system project (Last step of the "Build a Vitis Application"), even after I am changing the linker path to " ../src/lscript.ld"

[BogdanVanca]

Hello @Enthusiastic,

 

Can you please clean-up your project, rebuilt-it and after that send me the log file?

 

Best Regards,

Bogdan Vanca

[Enthusiastic]

Hi,

Apologies for the late reply.

Attaching the log file generated. 

.log

[BogdanVanca]

Hi @Enthusiastic,

 

Sorry for my late response. I cannot pinpoint anything wrong. Can you also send me a project archive? I will try to verify your setup, together with all your  project/source paths. Check bellow:

https://docs.xilinx.com/r/en-US/ug1400-vitis-embedded/Export-a-Vitis-Project

Make sure that you are including the build files. Thank you.

 

Best Regards,

Bogdan Vanca

[Enthusiastic]

Thank you for the reply.

Ya, I think even I will have to do a little digging around apart from the steps mentioned in the guide.  Appreciate your inputs.