Low Frequency Multiplying Phase Locked PLL for FPGAs and CPLDs.

[Joseph Kosednar]

Hello,

I would like to know if anyone needs a Low Frequency Multiplying Phase Locked Loop for their FPGA, CPLD designs with the following specs:

1.  Instant lock

2.  Small foot print

3.  2ns lock to leading edge

4.  10 bit multiplier value

5.  Clock in frequency = don't care

6.  Clock in frequency around 12MHz

7.  Input sample frequency 10Hz to 1000Hz auto ranging

8.  Stable

9.  Jitter -2ns

10. Generates LOCKED and OVERFLOW

If you could use this IP please let me know and how would you use it?