clock capable" pins Zedboard

[Dina_11]

Hi all

I want to use an external clock with zedboard 

I used in my expriments two zedboards.

First board generates PL clk 100MHz  and outputs this signal using "JA4" (which is AA9 on the FPGA) 

The second zedboard has as input clk using "JA4" (which is AA9 on the FPGA) and used to clock a counter but it's not working correctly 

I don't know if I used this pin correctly

# ----------------------------------------------------------------------------
# Clock Source - # "JA4"
# ----------------------------------------------------------------------------
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property PACKAGE_PIN AA9 [get_ports clk]
create_clock -period 10 [get_ports clk]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {clk}];

 

Please any suggestion

Thanks

[zygot]

"not working correctly" isn't terribly informative to anyone wanting to help.

When using the create_clock timing constraint it's a good idea to use the -name field to differentiate it from any other similar constraint in a design.

How are you connecting the boards? Clocks require particular attention to proper transmission line details.

Make sure that you have the correct pins connected as a starting point. Read through all synthesis and implementation messages and warnings.