FPGA output problem.

[Ludovico]

I'm using a Nexys Video Board with vivado/ SDK 2019.1. I made a basic MicroBlaze enviroment (the one the image shows) where i added a FPGA Custom IP (called TESI) with two axi-4 slave interfaces but one is not used yet, i just put it for later additio ns i'll need. The IP is a simple multiplier, i put the code of it and its axi connection in the attachments. The problem is that whne i test it in SDK/VITS the multiplier works only once: first time i put an imput i read the right output, but if i try a second or more time the result doesnt change and it remains the one of the first multiplication. I leave the SDK test code i use in attachment too. Where is the error in my project? thank you.

multiplierVHDL.txt AXImultiplier_VHDL.txt SDK_MultiplierTest.txt

[D@n]

Your first error comes from using Xilinx's broken AXI-lite slave template.  It's not protocol compliant, and will eventually lock up on you when you aren't expecting it to.

Your second problem is reading from the base address the second time instead of the base address plus four.

Dan