dcwestcott Posted November 4, 2021 Share Posted November 4, 2021 (edited) I have the following that does not work in Xilinx Vivado Simulator 2019: `ifdef FPGA 'define MAX_MEMORY 1024 `else // ASIC `define MAX_MEMORY 2048 `endif I've seen posts that say you can not do this, but Is there a structure I can use that will do this function without manually controlling parameters? Edited November 4, 2021 by dcwestcott more detail Link to comment Share on other sites More sharing options...
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