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ignored `define statement

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I have the following that does not work in Xilinx Vivado Simulator 2019:

`ifdef FPGA

'define MAX_MEMORY   1024

`else  // ASIC

`define MAX_MEMORY 2048


I've seen posts that say you can not do this, but Is there a structure I can use that will do this function without manually controlling parameters?

Edited by dcwestcott
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