ignored `define statement

[dcwestcott]

I have the following that does not work in Xilinx Vivado Simulator 2019:

`ifdef FPGA

'define MAX_MEMORY   1024

`else  // ASIC

`define MAX_MEMORY 2048

`endif

I've seen posts that say you can not do this, but Is there a structure I can use that will do this function without manually controlling parameters?

Edited November 4, 2021 by dcwestcott
more detail

[zygot]

In Verilog you can use localparam like this:

'ifdef FPGA
  localparam MAX_MEMORY = 1024;
'else
  localparam MAX_MEMORY = 2048;
'endif

It's so easy to confuse Verilog syntax with C syntax.. for me at least.