I noticed some strange behaviour while trying to make a risc-v core run on the arty. When doing a power-on, the reset line will toggle over a period of about 4 seconds. I noticed something strange so decided to connect a logic analyser to the breakout pin for the reset line on jumper "J8" and got the following trace. I get the exact same behaviour every single time, it's not random. I looked at the schematic and cannot see the CK_RST line being connected to anything other than the FPGA that might explain this behaviour. It seems that the last 6 occurrences of the reset line being pulled low are 650ms apart. The trace directly below is the VCC3V3 line on jumper "J8" which I probed to eliminate any issues with the power supply, as the CK_RST line is being pulled up by this rail through a 10K resistor, as the trace show the power is stable. Why is this happening?
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Ryno
Hi,
I noticed some strange behaviour while trying to make a risc-v core run on the arty. When doing a power-on, the reset line will toggle over a period of about 4 seconds. I noticed something strange so decided to connect a logic analyser to the breakout pin for the reset line on jumper "J8" and got the following trace. I get the exact same behaviour every single time, it's not random. I looked at the schematic and cannot see the CK_RST line being connected to anything other than the FPGA that might explain this behaviour. It seems that the last 6 occurrences of the reset line being pulled low are 650ms apart. The trace directly below is the VCC3V3 line on jumper "J8" which I probed to eliminate any issues with the power supply, as the CK_RST line is being pulled up by this rail through a 10K resistor, as the trace show the power is stable. Why is this happening?
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