VexRisc on Arty A7-35T - scala design cpu & add instruction & jtag debug sharing

[fatalfeel]

internal jtag eclipse setting:
https://www.mediafire.com/view/cwqifkpv4d27rgk/artya7-35t_internal_eclipse00.png
https://www.mediafire.com/view/jbd9r7f7rcc3y66/artya7-35t_internal_eclipse01.png
https://www.mediafire.com/view/fo5tlqccr8kijmg/artya7-35t_internal_eclipse02.png
https://www.mediafire.com/view/l81x5g1i4osxr3h/artya7-35t_internal_eclipse03.png

demo:
https://www.mediafire.com/view/tm67r0tv1vwe4il/artya7-35t_internal_demo00.png
https://www.mediafire.com/view/iua7omk5bittf69/artya7-35t_internal_demo01.png
https://www.mediafire.com/file/ecp5jjy2n6effxc/arty_internal_jtag.mkv

using Agent-proxy terminal, No minicom, usb log and usb jtag debug at the same time
1.
git clone git://git.kernel.org/pub/scm/utils/kernel/kgdb/agent-proxy.git
cd agent-proxy
make
~#./agent-proxy 4440^4441 0 /dev/ttyUSB0,115200

2.
open another terminal
~# telnet localhost 4440    //now connect to target console

///////build step///////
https://fatalfeel.blogspot.com/2013/12/risc-v-on-arty-a7-35t.html

Edited October 12, 2021 by fatalfeel