ARTY A7 - Bringing in an external 10 MHz clock to differential Inputs ?

[PeterModbury]

Hi FPGA experts 

Regarding - ARTY A7 - Bringing in an external 10 MHz clock to differential Inputs ? A XDC problem? 

An external 10 MHz clock is required  to be brought in on a differential   input. The PMOD A,B,C & D inputs are not differential . Can the clock be brought in on the ...

##ChipKit Single Ended Analog Inputs
##NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5). 
##      These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19].

#set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0]# Ground??
#set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0] ##,- Clock

Is this beyond the ARTY A7 board?

Is the capability not extant on the ARTY XDC file ?

Look forward to comments,

regards,

Peter. 

[zygot]

The Arty A7 has no user inputs connected to FPGA IO banks powered by a Vccio that supports any Xilinx differential IOSTANDARD.

The exception is TMDS33, and that requires 50 ohm termination, which is unlikely to be compatible with your external clock source. Of course, what you need to do is start with the logic specifications for your external clock.

One possibility, likely the best, is to use an external circuit that has differential inputs that are compatible with your clock source and puts out a 3.3V CMOS or TTL single-ended signal. There are a number of relatively easy to use differential to single-end or single-ended to differential components available for a number of differential logic families. For a 10 MHz clock you could use either the so-called high speed 'differential' PMODs or the regular slow speed PMODs. The last piece of the puzzle is finding a PMOD header pin that is connected to a clock capable FPGA pin. Fortunately, Digilent's schematics contain the FPGA pin names so that you can identify clock capable pins. Inside the blocks representing the IO banks look for any internal name having SRCC or, preferably, MRCC in it. Just start with the PMOD connector page and find the signal name on the IO bank page where that signal name get connected to an IO bank.

It's possible to specify an IOSTANDARD that your board cannot support if your constraints file doesn't have conflicting IOSTANDARD constraints for different pins on the same IO bank. The results will be confusing at best. Simply using an IOSTANDARD constraint doesn't allow any particular logic type to be used, whether you get bitgen errors or not. You need to go through the schematic to see what the selection of IOSTANDARD is available for your board design.

Termination on the XADC connector pins make it unsuitable for a 10 MHz clock, even if it were possible.

Can you connect an external clock to a non-clock capable pin and use it to clock logic in your FPGA? Yes. This is not a recommended practice for a number of reasons and you will get a bitgen error warning about it. You can over-ride the error by adding an additional constraint. The only reason to do this is when someone messed up the board design and there is no other option... such as when a component on the board has been connected to the wrong IO bank. I could argue that every FPGA board that Digilent has designed containing a high speed differential PMOD header falls into the category of bad design....

Please read through the Xilinx Series 7 SelectIO reference manual for information on how to use the FPGA IO.

Edited September 7, 2021 by zygot

[PeterModbury]

Hi  Zygot,

thank you for your response and concise response. My concern was it possible and I was missing something . You answered  my concern, the ARTY A7   can not input a 10MHz Ref . You have provide me with a back ground task of selecting a suitable board able to route a Ref into the clocking back bone / MRCC.  I had a look for a comparison matrix of  board capability, but nothing  obvious on the  DIGILENT web site, so will examine the different board types in detail.  

My immediate requirement can be met using a less elegant alternative approach.

Thank you "Xilinx Series 7 SelectIO reference manual" recommendation - I now have and will digest. 

Thank you  for your assistance,

Regards,

Peter. 

[zygot]

Sadly, Digilent's errors concerning true differential capability is not an outlier. Methinks that there's a lot of mindless board design copying going around. I have no explanation as why so vendors are making the same mistake. No one should design or layout a board who hasn't mastered the basic Xilinx clock and IO references... at a minimum.

I really don't know of a low cost board that is designed properly to use the differential IO capabilities for user GPIO on accessible headers. This isn't even a problem specifically to Xilinx based boards.

Now, Digilent does have boards with the FMC connector that have user selectable Vccio for the bank where the GPIO is connected. They also do a reasonable job with n/p pair length matching. Unfortunately, the FMC connector is not very user friendly for the average student or hobbyist to use. Ideally, you'd want to use internal termination for differential inputs, but this requires HP IO banks. Artix doesn't have those. Kintex does. There aren't any cheap Kintex boards that I am aware of. There also is a dearth of FMC mezzanine cards available. Xilinx makes an FMC debug card but all of the FMC differential signals are layed out as single-ended ( not length matched much less actually as differential signals ). It's a mess. I suspect that what vendors do is have a hands on approach to board design for the hard stuff like DDR memory and then let the auto router do the rest with the IO connectors getting little attention. There's no technical reason why even inexpensive FPGA boards couldn't have 1 IO Bank at 2.5V and used 2mm headers for user access.

There is the SYZYGY standard which could resolve the problem. All that needs to be done is for an FPGA board vendor to seriously commit to it. I'm not aware of one that has to date.

But now you know what to look for and where to find good technical information. Use that Document Navigator tool that gets installed with Vivado.

Edited September 8, 2021 by zygot