CMOD-A7 35t crystal frequency

[xzsawq21]

Hello

I want to buy a CMOD-A7 35t board. how much is the crystal frequency on the board? 12MHz? if so can I upgrade it? (I want to use the PLL), I checked the schematic and I only see a 100MHz crystal.

Thanks

[Guest]

The crystal provided is 12 MHz, as you say.

While this is out of spec for the FPGA's PLLs (F_IN range: 19 to 800  MHz), it is within spec for the MMCMs (F_IN range: 10 to 800 MHz). I have successfully generated fast clocks (> 100 Mhz) on the CMOD modules using the provided crystal, without any issue.

See Xilinx DS181, tables 37 and 38.
 

 

[xzsawq21]

3 hours ago, reddish said:

The crystal provided is 12 MHz, as you say.

While this is out of spec for the FPGA's PLLs (F_IN range: 19 to 800  MHz), it is within spec for the MMCMs (F_IN range: 10 to 800 MHz). I have successfully generated fast clocks (> 100 Mhz) on the CMOD modules using the provided crystal, without any issue.

See Xilinx DS181, tables 37 and 38.

Dear

Actually in my application, I measure the frequency of a pulse (the pulse is the output of an encoder), for example 40kHz then I should generate a 150Hz or a 200Hz pulse. Thanks

Edited September 3, 2021 by xzsawq21

[zygot]

2 hours ago, xzsawq21 said:

Actually in my application, I measure the frequency of a pulse (the pulse is the output of an encoder), for example 40kHz then I should generate a 150Hz or a 200Hz pulse.

Perhaps I don't understand what you are implying. Do you want to create a clock less than 12 MHz?

BTW, the CMOD-A7 has a number of clock capable GPIO pins so really you can use any external clock frequency your heart desires by connecting a 3.3V IOSTANDARD compatible clock source to one of the appropriate pins..

As for measuring a pulse width, the higher the clock that the logic runs at the higher the resolution of the measurement that you can make. The same is true for generating pulses.

Edited September 3, 2021 by zygot

[xzsawq21]

13 hours ago, zygot said:

Perhaps I don't understand what you are implying. Do you want to create a clock less than 12 MHz?

BTW, the CMOD-A7 has a number of clock capable GPIO pins so really you can use any external clock frequency your heart desires by connecting a 3.3V IOSTANDARD compatible clock source to one of the appropriate pins..

As for measuring a pulse width, the higher the clock that the logic runs at the higher the resolution of the measurement that you can make. The same is true for generating pulses.

I want to control a stepper motor, in my application, I capture a pulse signal from a source (consider 40KHz) then I should generate a 30Hz or 50Hz pulse signal.

[zygot]

You can certainly do that with logic clocked at 100 MHz, 50 MHz, or even 12 MHz. Usually stepper motors involve quadrature signals, though this depends on the driver design. You don't want to try driving a stepper motor directly from FPGA IO pins. Somehow, I think that I'm still not understanding the comments about pulses with repsect to your original question about external clocking.

[xzsawq21]

On 9/4/2021 at 4:10 PM, zygot said:

You can certainly do that with logic clocked at 100 MHz, 50 MHz, or even 12 MHz. Usually stepper motors involve quadrature signals, though this depends on the driver design. You don't want to try driving a stepper motor directly from FPGA IO pins. Somehow, I think that I'm still not understanding the comments about pulses with repsect to your original question about external clocking.

I have a stepper motor driver that generates suitable pulses for a stepper motor, but this driver wants an input clock. I generate the clock with a FPGA. the frequency of the clock determines the speed of the stepper motor.

in my application I capture a pulse signal from a source (consider 40KHz) then I should generate a 30Hz or 50Hz or 100Hz pulse signal to control the speed of the stepper motor.

 

Edited September 5, 2021 by xzsawq21

[zygot]

Sorry, I misunderstood the reason for mentioning the stuff about the pulses... guess I misunderstood your original question as well.

Just make sure that your stepper drive signals hare compatible with 3.3V logic using whatever IOSTANDARD you choose to select. I suggest that you select a SLOW slew rate on your outputs if you are connecting a cable or wires between the stepper drive and your FPGA GPIO header.