Understanding Zmod ADC 1410 Low Level Controller IP input frequencies

[tsarquis]

I'm trying to understand how to choose the input clock frequencies of the Zmod ADC 1410 Low Level Controller IP. The IP has two input clocks: the system clock and the ADC clock. According to the controller guide, the prior has to be 100 MHz and the second one 400 MHz, and there is not any much discussion about that.

So, like this, I would sample two analog input signals at 200 MSPS each one. The guide also says that the 16 bit output channel is  synchronous with SysClk (100 MHZ).

If I'm sampling at 200 MHz, why is the output channel refreshed at 100 MHz? I know the IP has some FIFOs but, wouldn't they fill and start to lose data? Right now it has no sense to me 

How can I change the sampling frequency? Whenever I change one of the two clock frequencies, the ADC starts to behave in a not proper way, even if I configure the clocks to 10/40 MHz.

I think my doubts have to do with my missunderstanding of the AD9648 SYNC signal, which is used for ¿dividing the ADC clock and sample at 400/X MHZ? (X=1,...,8)

 

[zygot]

The AD9648 has 2 speed grades as you noted from the datasheet, with 125 Mhz Fs being the highest sample rate. There's no sampling at 200 MHz.

The device has one clock input that can be up to 1 GHz. It has an internal clock divider to provide a suitable Fs from any input clock within the specified range. The SYNC signal allows for synchronizing the Fs sample clock across multiple AD9448 devices. I also allows for phase compensation. With the Eclypse-Z7 you have the potential for up to 4 channels of ADC with a synchronized Fs clock.

The device has a lot of programmable options and the default low level SPI controller automatically configures the device for one of many operating states.

The writeup for the ZMOD1410 design is pretty comprehensive. This pod doesn't provide for an external clock input, nor does the Eclypse-Z7 so users should stick with the clocking scheme provided for in the released interface IP. Since, you can't use an external system clock source, there's no point in changing something for which the pod is designed for. An exception might be if an Fs of 100 MHz is inappropriate for some reason and you need to select a slightly different sample rate.

As far as the other modes are concerned, you need to understand the control registers bit functionality. It might very well be useful to change the output code or use the test waveform function.

If you want to work with data samples that are less than 100 Mhz you can decimate and or interpolate to get to a desired sample rate without changing the clocking scheme.

Edited September 1, 2021 by zygot

[zygot]

125 MHz isn't an option for the ZMOD1410 as it uses the slower speed grade ADC. You really aren't supposed to change the sampling rate for these ZMODs, as I've tried to explain previously.

If you want to work with 25 MHz samples, then you should get 100 MHz samples from your ADC and decimate by four to get to your target sample rate. You can throw away 3 of every 4 samples to do this, or better yet do what's called a sum and dump filter that provides the average of four samples at a 25 MHz rate. Depending on how you do it you can increase the ADC data bit width ( resolution ). This is a common practice. It's possible to decimate to a lower Fs than desired and also integrate samples up to achieve a wide variety of system Fs rates. All of this could be done in the PL using HDL or even in software during post processing. This is frequently done in audio where there is a wide variety of industry sample Fs rates and conversion between them is a common requirement. BTW there are numerous DSP techniques for handling Fs rate conversion. The ZMOD1410 is a nice pod for learning how to implement DSP in either hardware or software.

Changing the ADC sample rate requires changing the clocking upstream in your design, so you usually don't want to do that. Everything about the ZMOD1410 is optimized for an Fs of 100 MHz so you don't want to change that. The ZMOD 1410 is designed to be a general purpose converter pod. Normally, the analog front end of an ADC in an embedded system is highly tailored to be optimized for a particular purpose. Of course, the ADC design and Fs range have a large part in overall design flexibility.

I really don't know of any other general purpose ADC module, other than the ADC1410, that's designed to work with an FPGA board and is so well thought out, and flexible. It's really well designed for it's intended audience. My only major quibble, and this is really a system issue, is the lack of an external clock input to the FPGA.
It's rare that I practically gush with enthusiasm over educational level FPGA products. The ZMODs are in that class. Now if only Digilent would deign a decent FPGA board to showcase the Series 7 family and SYZYGY standard so that students and advanced users could implement their design concepts without unnecessary restrictions.

Edited September 7, 2021 by zygot

[tsarquis]

Okay, I've taken a look at the AD registers map and some thing are now clearer, and some others are not 

What's the point in working only with this two Fs?
Personally, I need to choose one specific Fs, let's say, 20 MHz, for aplying undersampling, and this scheme seems very unflexible...

Suppose that I choose to work with the 125 MHz Fs: the IP core will still be refreshing the output data at 100 MHz.
In that case, I do have to change the sysClk from 100 to 125 MHz? I should also change the adcClk and/or the AD clock divisor value to get a result of 125 MHz?

 

Edited September 6, 2021 by tsarquis

[tsarquis]

It would be nice, at least for students like me, having this short clarification in the pod IP core user guide.

I was thinking in using a lower Fs for power consumption reasons, but it seems I won't be able for doing that 

Thanks again, @zygot. I'll work with the only Fs possible and investigate how to properly achieve my undersampling Fs by decimating.

 

[zygot]

There are a few nice ADC devices in the 2-20 MHz Fs range but I'm not aware of any PMODs that use any of them. That's one problem with constraining the user IO to PMODs. If no PMOD exists to meet a particular need then it's hard or impossible to do those projects with the board. I'd prefer better options for connecting external circuits but I don't make FPGA boards.

I agree that for the educational market customers likely don't have the experience to ask the proper questions in order to make a wise purchase decision so the sales blurbs should be clearer about any limitations. I don't think that low power operation is a matter for concern. The Eclypse-Z7 with two pods onboard don't consume that much energy and are designed to be used in a lab or desktop environment.

Having converters that sample at a higher than desired rate isn't always an undesirable thing or uncommon in real-world applications.

Edited September 7, 2021 by zygot