I am considering purchasing a Nexys Video dev board soon, but I have noticed the HDMI port is not connected to the GTP ports on the FPGA, just the standard IO ports. So I am wondering, can this board do 1080p 60fps with 24-bit RGB colour?
According to this screen shot from the HDMI demo on the digilent website it appears that it can but I’m not sure how??
I believe the HDMI standards states 1080p 60fps with 24-bit colour (8- bits per colour) requires 4.46 Gbps.
The Artix-7 standard IO is only 950 Mbps for LVDS at 2.5v, so I presume the 3.3v TMDS will be a bit faster, but not fast enough for 1080p60, as over 3 differential pairs (TMDS 0-2) would be a total theoretical limit of 2.85 Gbps.
So how can the Nexys video do 1080p at 60fps with 24-bit RGB colour over HDMI? As I’m not really seeing a clear cut answer as to how the demo seemingly accomplishes this.
It looks like it should not be possible, but the digilent demo says otherwise. Anyone care to explain how this is accomplished?
I can see the FPGA connects to a TI “HDMI Hider” (as it’s called by TI), but that seems to do little more than improve the signal integrity before being passed on.
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Mario875
Hi all,
I am considering purchasing a Nexys Video dev board soon, but I have noticed the HDMI port is not connected to the GTP ports on the FPGA, just the standard IO ports. So I am wondering, can this board do 1080p 60fps with 24-bit RGB colour?
According to this screen shot from the HDMI demo on the digilent website it appears that it can but I’m not sure how??
I believe the HDMI standards states 1080p 60fps with 24-bit colour (8- bits per colour) requires 4.46 Gbps.
The Artix-7 standard IO is only 950 Mbps for LVDS at 2.5v, so I presume the 3.3v TMDS will be a bit faster, but not fast enough for 1080p60, as over 3 differential pairs (TMDS 0-2) would be a total theoretical limit of 2.85 Gbps.
So how can the Nexys video do 1080p at 60fps with 24-bit RGB colour over HDMI? As I’m not really seeing a clear cut answer as to how the demo seemingly accomplishes this.
It looks like it should not be possible, but the digilent demo says otherwise. Anyone care to explain how this is accomplished?
I can see the FPGA connects to a TI “HDMI Hider” (as it’s called by TI), but that seems to do little more than improve the signal integrity before being passed on.
Or am I missing something?
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