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coldfiremc's Achievements


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  1. I can make a support case, I have enterprise support
  2. Thanks @zygot. I have two nexys video boards and a Nexys A7 among other fancy RFSoC boards. I would like to follow this test designs. I have a Xilinx enterprise license, so I can open cases, and I use this MIG ip's too much in kind of critical applications to let nasty bugs to appear this way. If you can narrow those bugs, I would get some sort of official answer with Xilinx. One of the causes of the limited clocks for MIG is the fact that MIG generates inside its refclock and max PLL clock and divider options get very limited this way. Better designs use 2 clocks: one for data, and one for reference, coming from external oscillators. It would be neat to have more boards designed with 2 differential oscillators (can be cheap oscillators, there's no need to get oven controlled PLL's in domestic boards like digilent's)
  3. I learned how to edit those xml files. Can I push a new version to the digilent repo?. Can you after that push them to the xilinx board store?
  4. Some News https://support.xilinx.com/s/feed/0D52E00006wQfP7SAK?language=en_US There's some little details in the IP and interface definitions. I tweaked a little the Board file also, to fix clocks and not matching of the TMDS interface names. HDMI input has the same problem probably, so it's time to check it
  5. Check logs and implemented design to see if the block is optimized/deleted in some way
  6. I finally managed to interface this device. I used lots of documentation, but the most informative was the altera AN433 Application note, that details how to write and derive constraints to modify the STA behavior to time this type of devices properly. Thanks @zygot
  7. Ok I found something Interesting Despite the board file has the I/O pins defined for this interface (and an associated IP), Implementation fails because i/o pins are not fixed. This is very strange considering that to assign a pin explicitly is enough to fix the I/O mapping. This is the error (The ISERDES needs an explicit and fixed mapping) Here's the "anomaly" I will check this further, digging in the Board File. Probably it needs a little fix Greetings
  8. After developing a project with this board I noticed that this problem is not only affecting the DVI input IP, but also the clock wizards. Apparently the board file has some inconsistent names. Also the constraints for this IP are a little "Weak" and with a minimum modification, are not applied correctly. Please update the board files. A workaround for this is write constraints manually, but this is not always easy for block designs. Also there's other problem with rgb to DVI, input frequency is not updated accordingly, so this error appears [BD 41-927] Following properties on pin /rgb2dvi_0/PixelClk have been updated from connected ip, but BD cell '/rgb2dvi_0' does not accept parameter changes, so they may not be synchronized with cell properties: FREQ_HZ = 75000000 Please resolve any mismatches by directly setting properties on BD cell </rgb2dvi_0> to completely resolve these warnings. Also incorporating the clock generator inside the ip limit the IP seriously. I think that the integrated clock generator must be discarded to simplify design and allow proper clock settings.
  9. Hi I'm trying to use the RGB to DVI ip to acquire video, and I'm getting placement errors. if I unpackage IP, I, can't find any "conflictive" setting related to placement, in the sense that there isn't any physical pin reference at all and ISERDES instances look good. I'm providing the 200mhz ref clock to properly drive input delays and I'm not using any external constraint file. How can I fix or check that there isn't anything wrong? The board (and related configuration) being used is a nexys Video, and compiling with Vivado 2021.1. The rest of the design has a microblaze, some buttons and leds and the DDR3 memory controller. I'm using the latest IP version from the Digilent IP Repo. Thanks
  10. RGB to DVI is just about the physical interface and not the video signal itself. AXI4-to-video IP in fact supports interlaced video. The important part is to calculate properly the timings and setting a proper serial clock for HDMI with an external clock manager. You have to check if your FPGA has enough resources to do this, knowing that HDMI serial clock is a little high.
  11. Hi I have to interface an ADC for a project, and this ADC(ADS4225) fits the requirements. I'm planning to buy the development board and the needed adapter to connect it to the FMC port of a Nexys Video. However, I never interfaced a high speed DDR LVDS device before, and this device (and all of its class) need some signal adjustments to get the data links properly aligned. Can I get some guidance to implement input delays and DDR clock calibration? Thanks
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