coldfiremc

Thanks for reading and being eager to discuss this. Clearly those are proposed changes. This is just an aid to the usage, as these boards are aimed to students. The main functionalities remain equal. There was a bug in some board files that created a differential clock instead of a single clock. This sets that clearly in the presets. Using an XIT is precisely what I am using, however I am avoiding to set any value explicitly and moving everything to the board files or ip presets. Some parameters can be set and extracted from the board.xml, but is not clear how this is supported. Documentation from AMD/Xilinx lacks on this matter

@Viktor Nikolov I just posted a pull request that create those IP's and updates the board files to make it easier.

Made yet another pull request that updates the board files pull request link Changes are: Interfaces for DPTI, PS2, VGA (without clock) Updated board files for nexys video DPTI interface PS2 Interface DDR3 interface FMC interface I2S interface Display port interface Updated board files for nexys4ddr and nexys_a7 DDR2 interface Fixed clock interface Updated IPs AXI DPTI (now has the just created dpti interface) AXI PS2 (now has the just created at interface) AXI I2S (now has the I2s Interface) VGA(now has vga_rtl interface) HDMI_output(now its interface is properly recognized by block design/ipi) Added IP (basic tests done with the Viktor Nikolov setup) DDR3 (MIG based). A repackaged version that is fully compatible with block design/ipi. No longer Coregen dependant. Compatible with nexys video and Arty DDR2 (Same as above). Compatible with Nexys-A7 and Nexys 4 DDR There are open issues: No known way to pass more detailed parameters from board files (currently only LOC's) and clocks. Question opened at AMD/Xilinx Forums I2S is not that standarized. Does not support input/output. In the case of nexys video it must be treated separately FMC: Just implemented what already works for reference xilinx boards. I tested with my own setup, but clerarly needs more testing. The DDR IP's need more testingn (add a better example and testbench perhaps). The one included is the one from MIG7, but does not take advantage of IPI, nor any AXI test IP Hope @artvvb and other people review and feedback this small contribution.

Please share if you already tried it, or if there is something to fix

The pull request related to this is here https://github.com/Digilent/vivado-boards/pull/48

here is my fork of the ip repo https://github.com/ColdfireMC/vivado-library/tree/ddr2_ip_update note that depends on updated board files, available. You have to just connect them in a block design and they work. https://github.com/ColdfireMC/vivado-boards/tree/ddr2_board_update The boards working with this are Nexys4-DDR, NexysA7(all variants)

Hi Viktor I repackaged the MIG7 into a native IP (but jost for the ddr2 boards, ddr3 on the works) to make it work nicely with this setup. Hope that Digilent guys approve the changes in the repo

Hi I recently created a series of pull requests that addresses common issues with mig in nexys4 and nexys a7 boards. I repackaged the mig ip in a native IP that is just plug and play in the block designs. Also added a board interface and updated the rgb2vga IP. Please take a look to it Ddr2 board update by ColdfireMC · Pull Request #48 · Digilent/vivado-boards Ddr2 ip update by ColdfireMC · Pull Request #85 · Digilent/vivado-library

I can make a support case, I have enterprise support

Thanks @zygot. I have two nexys video boards and a Nexys A7 among other fancy RFSoC boards. I would like to follow this test designs. I have a Xilinx enterprise license, so I can open cases, and I use this MIG ip's too much in kind of critical applications to let nasty bugs to appear this way. If you can narrow those bugs, I would get some sort of official answer with Xilinx. One of the causes of the limited clocks for MIG is the fact that MIG generates inside its refclock and max PLL clock and divider options get very limited this way. Better designs use 2 clocks: one for data, and one for reference, coming from external oscillators. It would be neat to have more boards designed with 2 differential oscillators (can be cheap oscillators, there's no need to get oven controlled PLL's in domestic boards like digilent's)