Setting the IO voltage to 1.2V on Arty 35t

[Raj Kankula]

I would like to have an IO voltage at 1.2V instead of 3.3V on a Arty 35t CMOD board. I see from the datasheet that both the HR and HP IO banks can be configured to any voltage between -0.5V and 3.6V.

Is there a way to configure one IO bank to operate at 1.2V and other IO banks to operate at 3.3V on a Arty 7 35t eval board?

For example, say I want the IO pin U15(bank 14) to output 1.2V signals instead of 3.3V signals, can I do the following changes:

1. Disconnect the VCC3V3 supply voltage of IO bank 14.

2. Apply an external 1.2V on the VCCO_14 node.

3. Configure the IO bank 14 to have LVCMOS12 IO standard.

4. Configure the pin U15 to be an output pin and write a logic '1' on the pin.

 

 

[JColvin]

Hi @Raj Kankula,

Based on your screenshot I'm guessing you are referring to the Arty A7 35T rather than the Cmod A7 35T, but the answer remains the same. I do want to make a couple of notes/caveats up front though:

- Why not just use an external voltage level translator, such as the Pmod LVLSHFT (though to be fair that only goes down to 1.8V rather than 1.2V)? Any sort modifications done to your board would void the warranty on the board.
- U15 is not an I/O, but a power input pin, so you can't really configure it to output a voltage as such. You would instead use one of the I/O pins bank 14, listed on page 4 of the Arty A7 schematic, https://reference.digilentinc.com/_media/reference/programmable-logic/arty-a7/arty_a7_sch.pdf.

The short answer to your question is no, it is not possible to do this.

 

The long answer is how do you plan to even do this in the first place? Pages 102 and 103 of Xilinx's UG475 show the locations of the Vcco pins for each bank for an XC7A35T in a CSG324 package, but looking at a physical Arty board I don't know how reconfiguring what power rail that goes to those specific package pins is feasible.

That being said, if you did manage to get the rewiring done and make sure your grounding is good and follow Xilinx's listed Power-on/Off Supply Sequencing guidelines in DS181, adjust the bank voltage in the .xdc, and account for a number of other hardware design details that I'm unfamiliar with, then theoretically yes, this would work. You likely wouldn't be able to use any stock Pmods with Pmod header JC or any Arduino styled shields since those two sets of I/Os are present on bank 14 and I'm not aware of any off the shelf solutions that are compatible with 1.2 LVCMOS I/O standard, but the I/O pins would in theory operate at 1.2V as intended.

Thanks,
JColvin

[zygot]

If you look at DS180 Table 5 you will see a list of all of the Artix Device-Package options with HP IO Banks... none.

@JColvinprovided the correct answer; that is trying to modify your Arty/CMOD ???? board to use one of the 1.2V standards is a bad idea.

Perhaps you could provide a motivation for  wanting to do this and someone could point you in the right direction to achieve your goals. If you really want  an FPGA platform with an entire IO bank powered with Vccio = 1.2V you are better off buying a board that was designed to do that. There are UltraScale ZYNQ boards, like the Ultra96V2 board that has two 1.2V banks exposed to IO headers. The GPIO headers on the Mimas-A7 are attached to IO banks that are powered by 3.3V but you can change that to 1.2V by changing the value of one resistor.

Unfortunately, the dual power supply level-shifter approach isn't very high performance if that's what you are after and some of these level translators come with a lot of small print in the datasheet complicating their usage. But you can always design some sort of digital interface to make your 3.3V IO compatible with any other logic standard. That's the preferred way to do what you want.

You can't 'configure' an IO bank to have an IOSTANDARD. Depending on what Vccio voltage a bank is power with you can select from a list of IOSTANDARDs that are compatible with that voltage. Of course, there's more to it than that. Some logic standards require termination. But even if you have all of that correct there's still the issue of how the signal gets from the FPGA ball to some connector pin by a copper trace on a printed circuit board. If your FPGA platform is designed to support a given IOSTANDARD then you can, or should, be confident that you can implement a project with success.

[Raj Kankula]

Thanks for the response Jcolvin and Zygot.

@zygot: The motivation for wanting to do this change is: I want my arty 35t eval board to interface with a custom IC that has a 1.2V IO interface. By default, I see that the supply voltage for all the IO banks on the Digilent Arty 35t FPGA eval board are connected to 3.3V. I am looking for a way to operate the IO pins of the digilent arty 35t eval board at 1.2V instead of 3.3V. 

Based on your response, it clearly looks like the best option for me would be to use the Mimias A7 eval board. The supply voltage to IO banks 15 and 16 are adjustable on the Mimias A7 board.

[zygot]

30 minutes ago, Raj Kankula said:

The supply voltage to IO banks 15 and 16 are adjustable on the Mimias A7 board.

No... schematic signal labels can be deceiving. Just because a power rail is called Vadj doesn't mean that the user can adjust it.

I really am fond of the Mimas A7. Oddly, all of GPIO on the board is connected to the same power supply output which is 3.3V. As they spent a lot of time making well matched differential pairs in the PCB layout to the GPIO headers I wondered why they would do this. The answer is that the vendor is happy to take orders on special builds where all of the GPIO are some other voltage like 2.5,V 1.8, 1.5V etc. Fortunately, a user only has to replace one resistor to change the Vccio on the GPIO banks. It's not an easy changes but I managed to do it and now have 2.5V differential capability on the board. I suggested to someone at Numato Labs that a small change allowing the user to select Vccio would be a nice change for the next board spin. I didn't get an encouraging response. If they made just a few alterations in the design the Mimas A7 could be perfect platform. Sigh....

The biggest problem with the Mimas A7 might be finding one to purchase as COVID is a global problem especially for product vendors.

As the Arty only has 16 low speed ( < 10 MHz ) and 16 high speed IO I'm guessing that your interface has less than 16 wires. One way to go would be to make a custom board with dual power supply level converters, or 0 delay digital switches. Be careful of level converters that have complicated descriptions of how to use them as they tend to be low data rate and problematic for some applications.