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Xilinx Big Generation Error 324-Solution Needed



Please suggest a solution for the below mentioned error



"ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD). This maycause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts

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First, please double check that you have imported you XDC file into your project.  Once you've done that, then go ahead and double check that all of your top level inputs and outputs match signal names within your XDC file.  Once they do, and once each signal name matches with a location (can't double on those) and an I/O standard, these errors should vanish.


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