Questions about features of the Analog Discovery Pro devices

[Guest]

Hi,

 

I am looking at the Discovery Pro 3000 devices. They look like a very nice upgrade from the lower-end Analog Discovery 2. I have two questions regarding the functionality they offer:

1) Will it be possible to control them using the DWF SDK (and the Waveforms GUI) via the Ethernet port instead of the USB port? That would be very useful in our lab.

2) Is it possible to slave them to a 10 MHz reference clock (eg. via one of the trigger inputs), rather than having it use its own (less precise) builtin clocks?

If not I hope those features will be considered for whatever comes next .....

Cheers,
  Sidney

[attila]

Hi @reddish

1. Yes it can be controlled with the WaveForms app or with DWF SDK over USB or Ethernet.
The DWF SDK is also preinstalled in the embedded Linux, so custom app/script developed on the computer can be ported/run in the device.

2. No. I will try to add such option for ADP3000 but not sure it is feasible or what limitations it will have.
We are planning to have such support for next products.

[Guest]

Thanks, that's awesome news. Being able to talk to the Digilent devices via the network will be a big plus compared to using USB in our lab.

Really crossing my fingers for the 10 MHz clock reference feature. I think the challenge there (among other things) is that the pin where the reference clock enters the FPGA should be clock-input capable, and most aren't.

[attila]

Hi @reddish

The next software version will add reference clock IO for ADP.

The trigger IO is not on a clock capable pin. It is planned to be on the next products. This mostly affects the delay which is ignorable when compared to the external the wiring.

[attila]

Hi @reddish

It will require a reference clock around 20MHz.
The supported scaling is 1-8, like 8x10MHz = 80MHz or 8x12.5MHz = 5x20MHz = 100MHz or 5x25MHz = 125MHz or any arbitrary combination.
It is also working with up to 15x but this is out of the spec.

[Guest]

Awesome! Thanks a bunch for following up on this.

It's a pity that 10 MHz input can't be made to work, it's sort of a de-facto standard in labs that deal with high-precision timing. But to have at least some ref-clock input option is already a big plus.

As to the "clock capability" of pins, for me the concern is not delay, but jitter. Signals that feed into regular FPGA fabric rather than directly into the clock distribution network (as can be achieved with a clock-capable input) have to pass through CLBs, and their behavior introduces quite a bit of jitter, especially if they are shared with some active unrelated functionality.

I hope to get my hands on a ADP3000-series devices one of these days to test this feature. If that happens I will do some jitter measurements and report back.

[attila]

Hi @reddish

In the next software version I will allocate an additional PLL to be able to use scaling above 8x, like 10x10MHz

Thank you for the information.