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Will the Base-linux-master run the fpga?



Can hardware be added to the base-linux-master? Target is Cora Z7-10.

The supplied system, with added clock out, was synthesized with 2020.2 but it seems the fpga has no clock. Nothing is seen at the added clock output pin.

Perhaps this is not working with 2020.2, but 2018.2 only.

The steps are

Synthesize the BD in the base-linux-master. Add a clock output and synthesize again. Generate bitfile. All good.

Boot linux

Use Hardware Manager to program the fpga with the now 2020.2 synthesized block diagram from the base-linux-master project. Program succeeds, done LED is on.

Look for a new clock at the assigned output. It's the 100MHz passed through. No clock appears. 

Note the Cora Z7 is still running linux, only the fpga was programmed. Will the PS-PL clock be active? It is enabled in the configurator at 100 MHz. Is it even possible to load and run the fpga this way, with linux running on cpu0 already? How about a small program to enable the fpga clock, is this needed?

Thank you.

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4 hours ago, RobertFrye said:

Will the PS-PL clock be active?

During the boot, the PS-PL clock is configured by the First Stage Bootloader (FSBL). If the FPGA configuration used to generate the FSBL code has the clock active, it will be activated during the boot. Otherwise, the PS-PL clock remain inactive.

4 hours ago, RobertFrye said:

How about a small program to enable the fpga clock, is this needed?

I think it should be possible to enable the FPGA clock fclk0 and set its frequency from the Linux command line using the following commands:

echo fclk0 > $devcfg/fclk_export
echo 1 > $devcfg/fclk/fclk0/enable
echo 100000000 > $devcfg/fclk/fclk0/set_rate

It's also possible to do it from the C code by manipulating the SLCR registers SLCR_UNLOCK, FPGA0_CLK_CTRL and LVL_SHIFTR_EN. The information about these registers can be found on pages 1577, 1598 and 1689 in UG585.


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