mafiltenborg Posted March 13, 2021 Share Posted March 13, 2021 (edited) My name is Martin. I've worked as an embedded systems developer for +20 years. All the usual suspects like PICs and 8051 MCUs have been part of my work-life, in recent years accompanied by ARM and similar CPUs. I've previously dabbled with PLDs to do address-decoding and such in VHDL, but now I think it's about time I have a look at them EfPeeGeeAaas all the whizkids keep bangin on about. I've bought an Arty board. And a new and bigger harddisk to fit the accompanying Vivado toolchain on... The process has been reported on my blog if you want to read on. Halfway through my first example-project I find a need to ask, so TADAA - here I am, to pester y'all in the months to come. Cheers :) Edited March 14, 2021 by mafiltenborg add link to blog, describing first issue to work around MaxDZ8 1 Link to comment Share on other sites More sharing options...
JColvin Posted March 17, 2021 Share Posted March 17, 2021 Hi @mafiltenborg, Welcome to the Forums! Feel free to ask any questions that you may have in the FPGA section of the Forum. I did read through your blog post; the most current guides that we have available that is designed for Xilinx's Vivado+Vitis software is available here: https://reference.digilentinc.com/reference/programmable-logic/guides/getting-started-with-ipi. I also wanted to point out that the Pmod ports (which I believe is what you were referring to by proprietary GPIO pins in your blog post) are not proprietary. The specifications explaining what part of the Pmod style is available for download on it's main page here: https://reference.digilentinc.com/reference/pmod/start. Thanks, JColvin Link to comment Share on other sites More sharing options...
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