Genesys 2 issues on Matlab

[Claford V Lawrence]

I was trying to use matlab FIL feature with genesys2, and I was setting io ports as specified in the board constraints repository, then there was this error.

ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 33. For example, the following two ports in this bank have conflicting VCCOs:  
ETH_MDIO (LVCMOS15, requiring VCCO=1.500) and sysclk_p (LVDS, requiring VCCO=1.800)

 

There was a similar issue on the forum link. There was not a clear solution on how to resolve this issue however。

Any help would be greatly appreciated!

Here is the constraint generated:

create_clock -period 5.000 -name sysclk -waveform {0.000 2.500} [get_ports sysclk_p]
set_property PACKAGE_PIN AD11 [get_ports sysclk_p]
set_property IOSTANDARD LVDS [get_ports sysclk_p]
set_property PACKAGE_PIN R19 [get_ports sysrst]
set_property IOSTANDARD LVCMOS33 [get_ports sysrst]
set_property PACKAGE_PIN AF12 [get_ports ETH_MDC]
set_property IOSTANDARD LVCMOS15 [get_ports ETH_MDC]
set_property PACKAGE_PIN AG12 [get_ports ETH_MDIO]
set_property IOSTANDARD LVCMOS15 [get_ports ETH_MDIO]
set_property PACKAGE_PIN AH24 [get_ports ETH_RESET_n]
set_property IOSTANDARD LVCMOS33 [get_ports ETH_RESET_n]
set_property PACKAGE_PIN AG10 [get_ports ETH_RXCLK]
set_property IOSTANDARD LVCMOS15 [get_ports ETH_RXCLK]
set_property PACKAGE_PIN AJ14 [get_ports ETH_RXD[0]]
set_property IOSTANDARD LVCMOS15 [get_ports ETH_RXD[0]]

 

Many thanks in advance!
set_property PACKAGE_PIN AH14 [get_ports ETH_RXD[1]]
set_property IOSTANDARD LVCMOS15 [get_ports ETH_RXD[1]]
set_property PACKAGE_PIN AK13 [get_ports ETH_RXD[2]]
set_property IOSTANDARD LVCMOS15 [get_ports ETH_RXD[2]]
set_property PACKAGE_PIN AJ13 [get_ports ETH_RXD[3]]
set_property IOSTANDARD LVCMOS15 [get_ports ETH_RXD[3]]
set_property PACKAGE_PIN AH11 [get_ports ETH_RX_CTL]
set_property IOSTANDARD LVCMOS15 [get_ports ETH_RX_CTL]
set_property PACKAGE_PIN AE10 [get_ports ETH_TXCLK]
set_property IOSTANDARD LVCMOS15 [get_ports ETH_TXCLK]
set_property PACKAGE_PIN AJ12 [get_ports ETH_TXD[0]]
set_property IOSTANDARD LVCMOS15 [get_ports ETH_TXD[0]]
set_property PACKAGE_PIN AK11 [get_ports ETH_TXD[1]]
set_property IOSTANDARD LVCMOS15 [get_ports ETH_TXD[1]]
set_property PACKAGE_PIN AJ11 [get_ports ETH_TXD[2]]
set_property IOSTANDARD LVCMOS15 [get_ports ETH_TXD[2]]
set_property PACKAGE_PIN AK10 [get_ports ETH_TXD[3]]
set_property IOSTANDARD LVCMOS15 [get_ports ETH_TXD[3]]
set_property PACKAGE_PIN AK14 [get_ports ETH_TX_CTL]
set_property IOSTANDARD LVCMOS15 [get_ports ETH_TX_CTL]
 

Here is the constraint generated from KC707 ( which is officially supported by matlab ), and it didn't give an error

create_clock -period 5.000 -name sysclk -waveform {0.000 2.500} [get_ports sysclk_p]
set_property PACKAGE_PIN AD12 [get_ports sysclk_p]
set_property IOSTANDARD LVDS [get_ports sysclk_p]
set_property PACKAGE_PIN AB7 [get_ports sysrst]
set_property IOSTANDARD LVCMOS18 [get_ports sysrst]
set_property PACKAGE_PIN W19 [get_ports ETH_COL]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_COL]
set_property PACKAGE_PIN R30 [get_ports ETH_CRS]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_CRS]
set_property PACKAGE_PIN K30 [get_ports ETH_GTXCLK]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_GTXCLK]
set_property PACKAGE_PIN R23 [get_ports ETH_MDC]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_MDC]
set_property PACKAGE_PIN J21 [get_ports ETH_MDIO]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_MDIO]
set_property PACKAGE_PIN L20 [get_ports ETH_RESET_n]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_RESET_n]
set_property PACKAGE_PIN U27 [get_ports ETH_RXCLK]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_RXCLK]
set_property PACKAGE_PIN U30 [get_ports ETH_RXD[0]]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_RXD[0]]
set_property PACKAGE_PIN U25 [get_ports ETH_RXD[1]]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_RXD[1]]
set_property PACKAGE_PIN T25 [get_ports ETH_RXD[2]]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_RXD[2]]
set_property PACKAGE_PIN U28 [get_ports ETH_RXD[3]]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_RXD[3]]
set_property PACKAGE_PIN R19 [get_ports ETH_RXD[4]]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_RXD[4]]
set_property PACKAGE_PIN T27 [get_ports ETH_RXD[5]]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_RXD[5]]
set_property PACKAGE_PIN T26 [get_ports ETH_RXD[6]]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_RXD[6]]
set_property PACKAGE_PIN T28 [get_ports ETH_RXD[7]]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_RXD[7]]
set_property PACKAGE_PIN R28 [get_ports ETH_RXDV]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_RXDV]
set_property PACKAGE_PIN V26 [get_ports ETH_RXER]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_RXER]
set_property PACKAGE_PIN N27 [get_ports ETH_TXD[0]]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_TXD[0]]
set_property PACKAGE_PIN N25 [get_ports ETH_TXD[1]]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_TXD[1]]
set_property PACKAGE_PIN M29 [get_ports ETH_TXD[2]]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_TXD[2]]
set_property PACKAGE_PIN L28 [get_ports ETH_TXD[3]]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_TXD[3]]
set_property PACKAGE_PIN J26 [get_ports ETH_TXD[4]]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_TXD[4]]
set_property PACKAGE_PIN K26 [get_ports ETH_TXD[5]]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_TXD[5]]
set_property PACKAGE_PIN L30 [get_ports ETH_TXD[6]]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_TXD[6]]
set_property PACKAGE_PIN J28 [get_ports ETH_TXD[7]]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_TXD[7]]
set_property PACKAGE_PIN M27 [get_ports ETH_TXEN]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_TXEN]
set_property PACKAGE_PIN N29 [get_ports ETH_TXER]
set_property IOSTANDARD LVCMOS25 [get_ports ETH_TXER]
 

[zygot]

8 hours ago, Claford V Lawrence said:

ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 33. For example, the following two ports in this bank have conflicting VCCOs:  
ETH_MDIO (LVCMOS15, requiring VCCO=1.500) and sysclk_p (LVDS, requiring VCCO=1.800)

This is one of the easier errors to understand. All of the signals connected to an IO bank have to be assigned an IOSTANDARD that is compatible with the Vccio  voltage that powers that particular IO bank. How do you figure out what this is? The Genesys2 schematic will show this. Somewhere on the toplevel ports is a signal connected to bank 33 that has been assigned an IOSTANDARD that isn't consistent with the Vccio supplied to bank 33. The message points out the first two signals that are inconsistent. If you want to know what IOSTANDARDs are compatible with a particular Vccio you can refer to the Series 7 Select IO Reference Manual that Xilinx supplies in the Document Navigator. There are a number of LVDS IOSTANDARDs depending on the IO bank voltage.

Any named signal in the constraints that doesn't have an explicit IOSTANDARD constraint will be assigned a default value by Vivado. I've seen some pretty crazy default IO constraints from Vivado 2020.2. You can see all of them by opening the Implementation and looking at the IO Floorplan view.

The Genesys2 has a user selectable Vadj Vccio to a few IO banks that require attention depending on what voltage you set Vadj to but this isn't relevant to your bitgen error.

The Genesys2 borrows heavily from the KC705 for a number of external features but has a very different power supply design ( which is good ) and a different set of interfaces and IO bank assignments. The constraints for the two boards won't be the same for a given hardware implementation.

[Claford V Lawrence]

On 3/6/2021 at 9:31 PM, zygot said:

This is one of the easier errors to understand. All of the signals connected to an IO bank have to be assigned an IOSTANDARD that is compatible with the Vccio  voltage that powers that particular IO bank. How do you figure out what this is? The Genesys2 schematic will show this. Somewhere on the toplevel ports is a signal connected to bank 33 that has been assigned an IOSTANDARD that isn't consistent with the Vccio supplied to bank 33. The message points out the first two signals that are inconsistent. If you want to know what IOSTANDARDs are compatible with a particular Vccio you can refer to the Series 7 Select IO Reference Manual that Xilinx supplies in the Document Navigator. There are a number of LVDS IOSTANDARDs depending on the IO bank voltage.

Any named signal in the constraints that doesn't have an explicit IOSTANDARD constraint will be assigned a default value by Vivado. I've seen some pretty crazy default IO constraints from Vivado 2020.2. You can see all of them by opening the Implementation and looking at the IO Floorplan view.

The Genesys2 has a user selectable Vadj Vccio to a few IO banks that require attention depending on what voltage you set Vadj to but this isn't relevant to your bitgen error.

The Genesys2 borrows heavily from the KC705 for a number of external features but has a very different power supply design ( which is good ) and a different set of interfaces and IO bank assignments. The constraints for the two boards won't be the same for a given hardware implementation.

Thank you for your deailed explanation. I checked against the reference manual and vivado. Everywhere I looked, people use the same constraints without any such error.

For example, in openpiton's xdc, there is no explicitly setting any voltage.

And in the digilent's master xdc, their configuration is basically the same as mine.

I was wondering if you could please take a closer look at my problem. Thanks!

[zygot]

In the first link that you present in your original post the answer provided by @elodgwas this:

Bank 33 is a 1.5V-powered bank. Make sure sysclk is input, because only LVDS inputs without internal termination are compatible with any bank supply voltage. For more information, see ug471 from Xilinx.

All of the signal names referenced in a constraint file has to have matching names (case-sensitive) in the toplevel design entity port.

In the openpiton project that you mention resolving this will take some effort as the core support a variety of platforms, all having different constraint names and assignments. As to the remark about internal termination, this is a user user constraint that should match the physical board design and if not explicitly defined will resort to the "default" setting.... whatever that is. With Vivado 2020.2 I've seen some pretty strange default constraint settings that I have to change.

You might as well get used to the fact that FPGA tools and devices are complicated and that implementing any particular project with any particular tool version without running into hiccups is unlikely, no matter how well written the source is.

In your constraints:

set_property PACKAGE_PIN AD11 [get_ports sysclk_p]
set_property IOSTANDARD LVDS [get_ports sysclk_p]

In the official Genesys-2-Master.xdc:

#set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
#set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p

You haven't provided the toplevel port so I don't know the names. I suspect that there isn't a sysclk_p there. Even if it is your pin assignment appears to disagree with the official location assignments provided by Digilent.