Pradeep Posted March 2, 2021 Share Posted March 2, 2021 Hello everyone, I want to upload and debug software in the riscv core which uses a murax soc without using physical jtag adapter, but maybe by using some IPs and Xilinx Virtual Cable on my arty a7-100 artix 7 FPGA board Are there any documentations regarding the same? Thank you Link to comment Share on other sites More sharing options...
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