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Arty A7-RiscV-Murax Soc-Xilinx Virtual cable


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Hello everyone,

I want to upload and debug software in the riscv core which uses a murax soc without using physical jtag adapter, but maybe by using some IPs and Xilinx Virtual Cable on my arty a7-100 artix 7 FPGA board

Are there any documentations regarding the same?

Thank you

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