How to use an external clock drive cmod A7?

[tommytml]

I have a existed cmod A7-35T project which uses an internal clock. Now I'm asked to use an external clock to drive the cmod , so I just created a single-ended input clock port and connected it to a clock wizard and the clock wizard output would go to components like microblaze or other AXI components. But turned out cmod was still working without an external clock connection. It seems like cmod still uses its internal oscillator even though I let it use an external clock. I searched online and it says cmod only takes differential input clock signal and the resistor R80 which connects to the oscillator should be desoldered.  I'm confused right now. Can someone give any suggestions?

[zygot]

10 hours ago, tommytml said:

 I'm confused right now.

I'd agree. The CMOD-A735T has a number of MRCC pins assigned to the GPIO pins. You can use any of these to add an external clock. The SRCC pins are also OK but have some additional restrictions. You need to make sure that your constraints file assigns a location to the new clock input. Make sure that the names on the topleve entity port matches  exactly the name in the location constraint. You will need to add a clock timing constraint, unless you use an MMCM or PLL fed by the external clock pin and use the MMCM or PLL output clock(s) for your logic. In this case Vivado creates the timing constraint, and you don't want a duplicate as it confuses the tools.

Read all of the synthesis, implementation, and bitgen warnings and errors that VIvado produces when you generate a bitstream; and address the serious ones. A sign that you are doing something seriously wrong is finding out that you clock source isn't what you thought it would be,

Before you even try to add pins and clocks to  design you need to be familiar with the Seried 7 SelectIO and Clocking reference manuals.

[tommytml]

14 hours ago, zygot said:

I'd agree. The CMOD-A735T has a number of MRCC pins assigned to the GPIO pins. You can use any of these to add an external clock. The SRCC pins are also OK but have some additional restrictions. You need to make sure that your constraints file assigns a location to the new clock input. Make sure that the names on the topleve entity port matches  exactly the name in the location constraint. You will need to add a clock timing constraint, unless you use an MMCM or PLL fed by the external clock pin and use the MMCM or PLL output clock(s) for your logic. In this case Vivado creates the timing constraint, and you don't want a duplicate as it confuses the tools.

Read all of the synthesis, implementation, and bitgen warnings and errors that VIvado produces when you generate a bitstream; and address the serious ones. A sign that you are doing something seriously wrong is finding out that you clock source isn't what you thought it would be,

Before you even try to add pins and clocks to  design you need to be familiar with the Seried 7 SelectIO and Clocking reference manuals.

So CMOD-A735T does accept a single-ended clock signals and there's no need to desolder anything on the board?

[elodg]

Trouble with homework, @tommytml?

The FPGA is flexible enough to allow for a different clock input. The on-board (shared) oscillator produces a single-ended 12 MHz LVCMOS33 signal wired to pin L17 as described here: https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/reference-manual#oscillatorsclocks

However, you are free to assign the clock port in your design to a different pin on the DIP connector. Find the right pin in the schematic: https://reference.digilentinc.com/_media/reference/programmable-logic/cmod-a7/cmod_a7_sch.pdf

Xilinx documentation will tell you more which pins can be used as clock inputs: https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf#G5.309030

[zygot]

8 hours ago, tommytml said:

So CMOD-A735T does accept a single-ended clock signals and there's no need to desolder anything on the board?

yes. So, the good thing about the CMOD GPIO is that there are no series protection resistors like the standard PMOD IO pins. The bad thing is that you can damage your device very easily if you aren't careful. You need to do some sort of digital design analysis about the signal integrity of your external clock module connection and grounding. Single-ended drivers need a current return path. This brings up the question of how you are going to power your clock module. The CMOD only supplies 3.3V on the PMOD connector. This shouldn't be a surprise to anyone as your are responsible for doing competent digital design once you start connecting external components. But that's the purpose of the CMOD isn't it? I sure would like to make the CMODs better at supporting the needs of their target audience but alas I'm just a flea on the tail of the dog...

[zygot]

One more thought. I suggest using an MMCM or PLL between your external clock input buffer and your logic. That way you have a lock signal as an indicator that your clock really is connected to your design. The CMODs have 2 suitable LED indicators for this. I'd also suggest that you put in a 32-bit counter that free runs and tie one of the counter outputs to the other LED as a heartbeat indicator. For a 100 MHz clock count(24) works out pretty nicely. If the LED is blinking at a rate that you can calculate for yourself then you have a pretty good idea that your logic is beig clocked at near the correct frequency. LEDs have limited utility as a debugging indicator but in this case it's a pretty useful one.

I guess that I really had two thoughts to add...

[tommytml]

On 1/28/2021 at 5:04 AM, zygot said:

I'd agree. The CMOD-A735T has a number of MRCC pins assigned to the GPIO pins. You can use any of these to add an external clock. The SRCC pins are also OK but have some additional restrictions. You need to make sure that your constraints file assigns a location to the new clock input. Make sure that the names on the topleve entity port matches  exactly the name in the location constraint. You will need to add a clock timing constraint, unless you use an MMCM or PLL fed by the external clock pin and use the MMCM or PLL output clock(s) for your logic. In this case Vivado creates the timing constraint, and you don't want a duplicate as it confuses the tools.

Read all of the synthesis, implementation, and bitgen warnings and errors that VIvado produces when you generate a bitstream; and address the serious ones. A sign that you are doing something seriously wrong is finding out that you clock source isn't what you thought it would be,

Before you even try to add pins and clocks to  design you need to be familiar with the Seried 7 SelectIO and Clocking reference manuals.

Thank you for the suggestion. Turns out I just made a typo in the constrain file and once I correct it it's working as expected. It's really disappointing when you found the big issue is made by a small mistake.

[zygot]

17 hours ago, tommytml said:

It's really disappointing when you found the big issue is made by a small mistake.

They are also very often the hardest ones to find.