Verilog code working in simulation but not on board

[WajdiMuh]

i am trying to build a fifo buffer with different write and read clocks it is working in simulation but not on the board

the code is attached below

buffer.v

[zygot]

You didn't post your testbench HDL but this doesn't matter; your buffer isn't even close to being able to do what you want it to do, so I can tell you that it doesn't work in simulation either. Unfortunately, simulation is harder to do than design so be careful about what you are reading into your simulation results.

Understand that there's a difference between using FPGA resources like BRAM as storage and logic LUT as storage. This is especially true for structures that span multiple clock domains.

You need a better understanding of how to pass data and signals between clock domains. Dual clock FIFOs aren't for beginners. Even vendor provided FIFOs have issues. Once you start using multiple clocks in a design you need to understand how to write timing constraints to prevent the tools from making bad inferences about your design. The fact that you tried to implement your buffer in hardware tells me that you aren't ready to tackle this project. I'm not trying to offend you, just nudging you toward reality,

Both Intel and Xilinx have good reference material for writing HDLs to help thier tools  infer common structures like RAM, FIFO, counters, etc. You should familiarize yourself with the available vendor material. The Vivado-synthesis and Vivado-using-constraints references are good places to start.

Sometimes, it makes sense to answer a question by providing a follow-this-example code snippet. Sometimes, this isn't a very good way to help someone get to the point where they have the knowledge to be doing what they want to do on their own.

 

[zygot]

May I suggest that you start off trying to get a one clock version of your design idea working as a first step.

This may or may not be of interest, but it's my experience that jumping ahead of your knowledge and skills to do more complex designs doesn't usually work out that well. What I mean by that is that part of the design phase is the verification effort which, at a minimum, includes writing 1 or more testbenches. Simulation skill improves with experience and is, to a degree, an art form. Beyond simulation is knowing how to test and debug your designs in hardware. In any project that involves doing something new to me I always have in the back of my mind, as I'm working on the design, a route to how I might test and debug the hardware. RTL implementations that are correct don't necessarily work on hardware. This could be due to a lot of factors. An incomplete understanding of the problem leads to an incomplete design and hardware is generally unforgiving of failure to get the details correct. It also could be not knowing how to use the tools properly.

So, what's a good indicator that you aren't ready to execute a design? One, would be implementing it on hardware and having no idea what to do when it isn't doing what you think that it should be doing. If a design seems to be working on hardware i the same way as the simulation this is not a guarantee that either the design is correct or that the simulation testbench is adequate.