Where Can I Get Help With Accessing th 256 MB DDRSL memory on Diligent Arty A7 -35 Board With Artix 7 FPGA

[jerremyhamston]

I need help with accessing the 256 MB DDRSL ram that is provided on the A7-35 Board. I plan to have more than one module access the ram.

I know that there is supposedly some IP available from Xilinx via the Vavado Web edition, which is the development software that I am using on my Linux system.

However, I have seen some serious criticism on this forum (Reddit) of the Xilinx IP; with some folks considering the IP very trouble prone.

I am not familiar at all now how to Implement logic on the Artix to access the RAM in such a way that multiple modules (each with its own always loop) accessing the ram. I do plan, however to have only one clock root using the 100 MHZ clock on the board.

I do not plan to productize my project; it is to learn as well as to have a piece of art that I can show off here in Bellingham, therefore, I am not planning to get my design certified by anyone.

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[zygot]

7 hours ago, jerremyhamston said:

I am not familiar at all now how to Implement logic on the Artix to access the RAM in such a way that multiple modules (each with its own always loop) accessing the ram. I do plan, however to have only one clock root using the 100 MHZ clock on the board.

It really shouldn't be a big global secret for figuring out how to use the iniquitous FPGA development board external memory for HDL only, standalone ( no processor ) multi-channel projects. If you spend enough time you will discover a few example demos from other vendors that might be a gateway to your constructing your own custom design. You don't need a Qsys with Quartus or to start with a board design with Xilinx to do this; it's just what the FPGA vendors prefer. I don't know any who are willing to help customers escape their walled garden design flow in order to use hardware meant for learning use DDR memory.

Some FPGA devices have a hard external memory controller in the device, and if it's connected correctly you can create higher performance multi-channel designs. Some FPGA devices don't have this so you need an all logic, lower performance implementation. I've seen FPGA boards with DDR requiring both if you want to make full uses of the board feature set. 

For Xilinx I'd recommend that you start with the MIG IP to get a single channel controller up and running. This IP doesn't actually get you a DDR ready application. You still have to write you own read/write logic to use the core. Once you've executed your first design, it's a lot easier to do variations and port the basis to other devices. Oh, and I strongly advise anyone doing this to use Verilog to implement the basic DDR controller core. You can always instantiate modules or components using one HDL in the HDL that you want to work with, though sometimes this comes with penalties.

It's about time that someone publishes a good tutorial for this but I don't have anything suitable as a jumping off point at the moment.

I'm someone who is willing to accept the notion that the cost of a moderate priced hardware board as a reasonable compensation to a board vendor willing to provide a good HDL demo so that users can learn how to use the stuff that comes with the board. I mean, these days you can spend a lot more for a poor excuse for a textbook that has little long term value. Really, should the purpose for selling this kind of hardware really be just to replicate a demo that can't be deconstructed and modified or should it be a teaching tool for FPGA development ( as opposed to restricting users to a design flow that is inherently designed to captivate them ).  Sadly, this doesn't describe the big vendors or their partners Terasic or Digilent.  Perhaps, you've given me something to add to my 2021 ToDO list...

The good news is that Xilinx external memory IP isn't full of script generated encrypted sources, as is the case for Ethernet MACs, though it is possible to slog through what is readable to glean hints on how to use the Ethernet PHY at least.

[zygot]

On 12/30/2020 at 1:24 AM, jerremyhamston said:

However, I have seen some serious criticism on this forum (Reddit) of the Xilinx IP; with some folks considering the IP very trouble prone.

I don't avail myself of that platform but in my experience over many, many years I can say that one is left with the impression that the general attitude of FPGA vendors with regard to their freely available ( and sometimes not free ) IP is that if a user finds a particular IP useful, then great, but everything is provided "as is". The concept of buyer beware applies in particular to free stuff.

Unfortunately, even basic IP that seems to work, or behaves in one way from tools version X might not in version Y or even X.y. Vivado FIFO IP comes to mind as it's the most recent to bite me in the keister.  Fortunately, you can usually get around flag and word count issues on the system level. 

If there's a bottom line to this it might be: "the user is ultimately responsible for designs and design verification". It's foolish to make your success dependent on handouts and other people's work, even if that comes from your FPGA vendor. The main problem is that unwary users need to do a lot of work to find these surprise sources of new tasks. I suggest assuming that vendor IP might be suitable for quick prototyping of a concept with the expectation that if you use it you should be prepared for the likelihood that you will run into problems and have to do some triage assessment as to whether you need to write your own IP or plug ahead with a work-around of your own devising.