AndyHook1970 Posted December 29, 2020 Share Posted December 29, 2020 Hi There, I am new to FPGA development and verilog. I have a Basys 3 Board and I and I am trying to synthesise the "Flip-flops to Build a Clock Divider" example shown on the Digilent website, but I keep getting this error :- [Synth 8-2576] procedural assignment to a non-register Q is not permitted I have attached my design and constraint files. I would really appreciate some help to get me over this first hurdle. Andy dff.v flipFlopDivider.v Basys-3-Master.xdc Link to comment Share on other sites More sharing options...
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