Is this the proper method of connecting the MIG DDR block for ARTY S7? (Yes, it does pass timing and passes a simple DDR3 test) The MIG interface was generated with CLKIN set as 100Mhz and System clock and Reference Clock set to No Buffer. clk_out1 is 100Mhz, clk_out2 is 200Mhz.
should sys_clock be used as a sys_ref_i clock?
If not what is the proper method be?
If this is correct why is there two clocks on the board? ddr_clock ans sys_clock
According to the MIG setup in the github for the ART-S7, clk_ref_i is connected to ddr_clk. how would this work if using a MicroBlaze?
Question
tcmichals
Is this the proper method of connecting the MIG DDR block for ARTY S7? (Yes, it does pass timing and passes a simple DDR3 test) The MIG interface was generated with CLKIN set as 100Mhz and System clock and Reference Clock set to No Buffer. clk_out1 is 100Mhz, clk_out2 is 200Mhz.
Link to comment
Share on other sites
0 answers to this question
Recommended Posts
Archived
This topic is now archived and is closed to further replies.