How to load input to my RTL module using PS and Vitis(or SDK)?

[Ian KIm]

Hello, I am beginner of zynq and i have a few questions.

 

I'm using Zybo Z7-20 board(zynq-7000) family) and i wanna test an example - 4_bit Adder module -  using PS & PL

 

My final project is limited on PL-only design because the the board has fewer switches, buttions, and MIO port.. etc that i want to implement

So i think i should use Block Design(VIVADO) and try load input, output to RTL module via PS section.

 

i have some research about that but i don't sure that I understand exactly how to transfer data to my RTL module.

 

My understand is  data transfer should follow these step:

SDK C code -> PS -> AXI-GPIO -> RTL module (load input)

 

RTL -> AXI-GPIO -> PS -> view output in terminal

 

is that right and It is possible solution?

 

or how should I load data to my RTL module via PS? (using BRAM controller? custom IP?,,, or other solutions?)

 

I'm so confused to assign IN,OUT signal to my RTL module..

 

Here's my VIVADO block design

 

best regards.

[zygot]

If you open each of the AXI-GPIO elements in your board design you can assign them as all input, all output or inout. If they are all inout then you can have your PS software application assign a direction to any of the GPIO pins individually. I haven't used Vitis yet but the SDK allowed you to import example software projects for your various hardware interfaces as a guide. For a simple design like this you'll find that it's fairly straight-forward, after you've done it once.