# What are the preferred method of varying sampling frequency?

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What I'm trying to accomplish is to vary the ADC sampling frequency according to the mains input frequency. my input frequency is 50Hz and want to get 64 samples for a start which would results in 3200Hz sampling frequency. Since main frequency are likely to vary from time to time, I'm looking for ways to vary the sampling frequency according to the input frequency. I have been suggested to use LUT, which will use around 400 LE or register as the frequency varies between 48-52 Hz at most in 0.01 increments due to electricity standard. I'm wondering if this is the best method or there are better solutions.

Kind regards

Edited by Liur1996
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Hi,

I'd start with a counter at 100 MHz to divide by 31250, giving 3200 Hz = 64*50 Hz.

The next closest setting is 31249, which gives 3200.1024 Hz or 1.6 Millihertz offset to 50 Hz. Most likely, this is "close enough"?

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Not understanding what it is that you intend to achieve my initial reaction is that this seems a bit weird. What's the theory behind trying to fix a number of samples to a mains AC period? What you are describing would seem to introduce more problems than it solves.

Might it be a better idea to have a fixed Fs for your signal of interest and also track the mains period simultaneously?

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I think my approach would be to first lock a PLL to a sampled copy of the 50Hz signal.  You can then use the phase of the locked PLL to drive the sample rate.  (PHASE * 64 == sample number, when it changes--sample)

There are a lot of pitfalls associated with doing this, and I think @zygot is subtly hinting at some.  To answer @zygot's why question, let's assume that a nation's 50Hz signal is (broadly) driven from a highly accurate clock.  This is close to the case in the US, although in the US the tracking is probably not good enough for driving a sample clock even though the long term stability is quite accurate.  Another useful reason might be locking disparate A/D's across a large distance, without needing to pass timing from one A/D to another.  Yes, there are still more pitfalls here--like getting sample to sample timing lock, so that's still going to be a remaining issue you might struggle with.

Here are some of the pitfalls I've struggled with when working a similar problem---locking a PLL to a GPS PPS input: 1) Just because the incoming signal is perfectly accurate, your local oscillator may not be accurate enough from one 20ms interval to the next.  (20ms * 50Hz = 1 ...)  I've measured accuracy on the order of less than a us when using an Arty-A7, so it's probably good enough for a 3.2 ksps digitizer.  2) You'll need to offload phase errors from the PLL across the whole 20ms interval.  I know I offloaded the entire phase error in my case immediately on the next PPS rise.  It made the logic easier to build, but might not be good enough for driving an A/D.

Dan

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Well, Zygot is subtly hinting at a number of things that is bothering him about this question.

For starters, the goal is 64 sample every 20 ms. That is a sample interval of 312.5us.  A cursory google for typical 50 Hz stability indicated that this might be .2% on a modern grid. That's a worst case deviation of about 40 us every 20 ms cycle. This is substantially lower than the sample interval. So this begs the question. What exactly is the point of all of this; because the answer to that question will drive any discussion about how to get to where you want to be.

Now, I'm sure that you can find places where power line stability is unusually bad. Remember that we are talking about spinning magnets, generally in the form of very large turbines... sometimes jet engines for quick short term high demand events.

To make matters worse we can think in terms of frequency stability or phase stability but this is application specific. If you start considering line frequency in terms of jitter then thisbegs the question: what kind of jitter are you worried about?

Basically, the question implies some sort of synchronization but doesn't suggest what you want to synchronize to. If we're talking about zero crossings ( 2 per cycle ) then by the time you measure the current cycle period it's to late to decide how many samples you want for that cycle. Just modulating the sample interval introduces more questions. And don't under estimate the difficulty in deciding what a zero crossing is much less detecting it. For AC loads we have to consider the implications of impedance. Are we talking voltage or current? Expecting the phase of both to happen at the same time is pretty naive if your equipment is connected to a real power grid..

This is one of those easy to think about hard to accomplish kinds of problems. A few thought experiments might be in order. Once you figure out what it is that you need to do then the real fun begins in trying to decide how to do it... and what the consequences of your methodology bring with it.

Edited by zygot
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On 8/24/2020 at 5:36 PM, zygot said:

Now, I'm sure that you can find places where power line stability is unusually bad.

OT: I think Barbara Dennerlein once discovered such a place playing Hammond organ on a generator-powered festival... almost in tune...

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The reference to Barbara Dennerlein is beyond my cloistered lifestyle ; but I get your point.

Sometimes a question suggests that a different problem than the one being asked is at the crux of the difficulty. It's a sense, analogous to the web crawler's spidey sense, that gets tingled every so often. It's a result of many years of experience. Sometimes the source of the question simply hasn't thought trough the problem. Sometimes it represents a naive understanding of the problem. You can't really solve a problem unless you understand it. Occasionally, you can have a naive understanding of the problem and still come up with an acceptable solution, but usually doing the work to more fully understand the problem eliminates those solutions from consideration.

I'm not suggesting that there's nothing to discuss here; just that a bit of digging is in order to better describe exactly what needs to be done and discuss possible solutions. It's unfortunate but more knowledge often impedes progress. Less knowledge produces quick results but not generally correct ones.

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On 8/23/2020 at 10:45 PM, xc6lx45 said:

Hi,

I'd start with a counter at 100 MHz to divide by 31250, giving 3200 Hz = 64*50 Hz.

The next closest setting is 31249, which gives 3200.1024 Hz or 1.6 Millihertz offset to 50 Hz. Most likely, this is "close enough"?

those was my first options to this problem, but I found people used lookup tables in their implementation rather than frequency division, maybe I just have it confused.

My project is to build a mains impedance analyzer that measure the magnitude and phase of a three phase power system, with those information then calculate the voltage, current, phase, frequency and RoCoF of the power system. Here the supervisor wanted to use the PLL to perform tracking like @zygot and @D@nsuggested, but my interpretation was tracking the signal only means the frequency different is shown but varying the sampling frequency still need to be done to maintain a 64 sample per cycle, which lead to my question of how can sampling frequency be efficiently varied.

our signal will be 50Hz to start with which will make it easy to track, the problem is after when we switch a load onto it, that is when we get the data for the power system.

the goal is to make sure the signal phase that enters the PLL section leave at the same phase even after going through the load so it maintains a clear signal. and the signal is voltage and current because these are the input we will get from mains.

I'm very thankful for your replies, I just need sometime to digest them.

Cheers

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10 hours ago, Liur1996 said:

My project is to build a mains impedance analyzer that measure the magnitude and phase of a three phase power system,

A number of companies, like TI and ADI, already have a portfolio of ICs that address the substance of your project. So, what's deficient with those options?

10 hours ago, Liur1996 said:

the problem is after when we switch a load onto it, that is when we get the data for the power system

Perhaps a bit of detail about what data you are talking about might help.

So, you obviously want to synchronize your data collection to something.... for a 3 phase mains load. What kind of load are we talking about?

One problem is that a typical PLL isn't designed to compensate on a cycle by cycle basis. This is why I'd suggest collecting all of the pertinent data as well as the mains frequency and phase in parallel and doing post-processing to achieve your measurements. That would seem to be the most robust approach.

I'm still not getting the rational for a strict adherence to 64 samples per cycle. As I mentioned earlier power companies need to maintain pretty good line rate stability. When you are introducing a new energy source capable of delivering MW of energy to an existing grid, frequency and phase alignment is pretty important. This might happen more than you think as generators are brought off-line for maintenance.

Phase and frequency analysis and measurements for power applications are a bit more complicated than for logic applications.

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I can see the reasoning behind 64 samples and matching the sampling frequency exactly ("cyclostationarity", you get an exact line spectrum).

A true analog PLL (with a VCO) may be overkill, though. You can simulate it purely in the digital domain as a variation of my counter scheme that adjusts the division ratio on the fly.

The main reason I'm saying "overkill" is that you can tolerate pretty high error in your sample timing thanks to the low frequency. For example, let's take the 10th harmonic of 50 Hz (500 Hz - 2 ms cycle time). If I derive the ADC clock by counting from 100 MHz base clock, I have a timing jitter of 10 ns. Relative to 500 Hz / 2 ms, this is an error of 0.002 degrees which isn't very much.

The bigger problem is probably locking in to the grid frequency to get the 1.6 millihertz offset from my earlier post away. But as said, that can be done with a digital PLL, strictly on the logic fabric (phase detector, loop filter, basic PLL theory).

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16 minutes ago, xc6lx45 said:

I can see the reasoning behind 64 samples and matching the sampling frequency exactly ("cyclostationarity", you get an exact line spectrum)

Well... perhaps. But this is load impedance measurement. I think that this is a lot more dynamic than you suppose. The simple analysis of AC power involves current, voltage and the phase relationship between the two which is impedance dependent. And don't forget about crest factor.. Imagine that your load is a couple large 3-phase motors attached to lumber saws.

But this raises another question. What is the goal for the application? Do you need 64 'instantaneous' measurements per cycle or generating a figure over a longer interval?

I well could be barking at the bottom of wrong tree here. I just think that this question is likely to be more complicated than it appears to be. If you are imagining a nice sine wave for voltage and a nice sine wave for current with some easy way to measure phase offset between the two then I suggest that this is somewhat naive.  Perhaps it doesn't make a difference.

This could actually be an interesting project. Power companies get paid for how much power a customer uses. They have a specific way to measure that. I know that you can buy equipment to compensate for highly reactive loads to lower you electricity bill. For the typical home owner this might not be so useful For a industrial customer you could save a lot of annual fixed costs by being smarter than your electricity provider.

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This is more of a uni project exploration, we are trying to get the analog discovery 2 take in the analog signal into ADC and then process it through digital PLL, so an out of phase signal from mains can be changed to a in phase signal before inputted into the a device. the number of sample can increase to 128 or 256 per cycle, but 64 is just a starting point. we want to be able to correct the phase difference after 1 full cycle of sampling rather than a figure over longer interval as the device is used to correct the phase difference rather than creating a figure of the phase difference. our supervisor suggested windowing the samples to get a instantaneous measurement.

On 8/29/2020 at 3:33 AM, zygot said:

Well... perhaps. But this is load impedance measurement. I think that this is a lot more dynamic than you suppose. The simple analysis of AC power involves current, voltage and the phase relationship between the two which is impedance dependent. And don't forget about crest factor.. Imagine that your load is a couple large 3-phase motors attached to lumber saws.

But this raises another question. What is the goal for the application? Do you need 64 'instantaneous' measurements per cycle or generating a figure over a longer interval?

I well could be barking at the bottom of wrong tree here. I just think that this question is likely to be more complicated than it appears to be. If you are imagining a nice sine wave for voltage and a nice sine wave for current with some easy way to measure phase offset between the two then I suggest that this is somewhat naive.  Perhaps it doesn't make a difference.

This could actually be an interesting project. Power companies get paid for how much power a customer uses. They have a specific way to measure that. I know that you can buy equipment to compensate for highly reactive loads to lower you electricity bill. For the typical home owner this might not be so useful For a industrial customer you could save a lot of annual fixed costs by being smarter than your electricity provider.

your last paragraph is probably what our supervisor is hoping to achieve through this.

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