Nexys A7-100T errors with tutorial

[CarlosN]

Hi,

    I have a Nexys A7 100T board that I just started to check out using the 'Getting Started with Vivado' tutorial.  I installed Vivado v2020.1, on my Ubuntu 16.04 LTS workstation. All look good until the final report indicates the below 2 errors and 1 warning.  Please see the attached .vdi file for more context.  I have done a fair amount of searching, but have not found anything that I would want to commit to trying without the risk of bricking my new dev board.  I would really like to find out where I can get the information the error output suggests when it says 'Refer to the device configuration user guide for more information.'

    Many thanks for setting me on the right path,

 

Carlos N

 

blinky.vdi Nexys-A7-100T-Master.xdc blinky.v

[zygot]

I love it when the answers are easy.

All of the location constraints are commented out by default; that is they have a # character at the beginning of each line. You need to remove the leading # character from the appropriate lines. You will get errors if you try and set constraints for pins that aren't being used.

So, you ask, how do you know which lines to put into your project constraints? Well, every signal named in the port of your toplevel module has to have a pin location assignment at the minimum. Be aware that the spelling of these signal names in your HDL has to match exactly the names in your constraints xdc file. I always check the schematic to verify pin assignments against the constraints when using pins for the first time.

BTW Blinky is a good first step. In fact all of my designs have a free-running counter with an output pin tied to an LED as an indication that my logic is being clocked and that I didn't do something stupid with resets. Confession... I do something stupid with resets more often than I care to admit. Mostly, it's having modules wanting an active low and a few modules wanting an active high reset. As designs get more complicated the stupid mistakes seem to get easier to introduce into my designs.

Personally, I keep the Digilent Master Constraints file around as is in a /doc folder in my project directory, and then create a new version for each project that just contains pins that I am using.

[CarlosN]

Thank you for the quick response.  Unfortunately it only increased the number of errors in the output .vdi file. I checked both types of syntax for the led/LED name, capitalized and lower-case, while making sure both the constraints .xdc file changes matched the design source .v file. I know it's got to be a simple answer to a simple problem, as this is the basic 'Hello World' test case.  I think it more likely relates to having a newer version dev board with the latest 2020.1 version of Vivado. The tutorial is likely missing a key component.  Attached is the last iteration that includes all lower case syntax.

    I'll keep trying if I find something interesting in the Vivado help docs.

Carlos N

 

blinky.v Nexys-A7-100T-Master.xdc blinky.vdi

[zygot]

14 minutes ago, CarlosN said:

unfortunately it only increased the number of errors in the output

Well this is good... sometimes  more errors is a sign of progress.

You have one input and one output. You still have problems in your constraints:

You have a 1 bit led signal in your Verilog but a 16-bit led signal in your constraints. You assigned 16 led pins but aren't using any of them. Pick one of the potential led signals in the constraints, let's go with led[0] and comment out the others... then report back.

You have a choice here: either change the name in your toplevel module from led to led[0] or change the name of one of the 16 led signal in the constraints file to led. Be consistent throughout all of your design sources which include constraints. Not all choices will work out best as you develop your HDL skills.

[CarlosN]

Victory at last!

    Lots of learning curve remaining. Important to get in a good first step. Thanks!

[zygot]

Great! You'[ve take a first step. Now try something a bit harder. In light of what I've told you about using an LED as a clock and reset sanity check see if you can make blinky.v better by adding an asynchronous reset input to it and using that as a global reset for the design, including the counter.

Some Digilent FPGA boards have external hardware de-bounce circuitry. See if yours does. Then use a button as a reset. Figure out if the button is active high or low ( try and nail this on the first try ). Don't worry about conditioning your reset as it's not that important for beginning designs meant to learn how Verilog as synthesis works.