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Accessing the flash manually on the Anvyl


CPerez10

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Quoting from https://reference.digilentinc.com/reference/programmable-logic/anvyl/reference-manual#flash_memory:

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An FPGA configuration file requires less than 12Mbits, leaving 116Mbits available for user data. Data can be transferred to and from a PC to/from the flash device by user applications, or by facilities built into the iMPACT PROM file generation software. User designs programmed into the FPGA can also transfer data to and from the flash.

What makes you think it is only for FPGA configuration? Instantiate the AXI Quad SPI IP and map it to the pins called out in the RM and schematic.

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