XADC Bare metal code

[Clyde]

Is there an example of simple bare metal code for accessing the XADC?

This poster did it, but it wasn't what he really wanted:  

https://forum.digilentinc.com/topic/12613-program-code-on-petalinux/

Clyde

 

[mikewu4466]

Hi, can either one of you help me get started with using the XADC with the DRP and HDL (Verilog)? I got the XADC working using the AXI and code in the SDK, but I want to create modules that can take the data and process it serially. When I select the DRP interface on the XADC Wizard block on my block diagram and expand, I can see a bunch of connections that need to be made, it seems like my signals of interest are do_out for accessing the output. What serves as the inputs for the other connections? What tips do you have for getting started?

[zygot]

4 minutes ago, Clyde said:

It is curious that when configuring the ZYNQ, one can completely disable all of the peripherals.  

It's more that when designing a board using a ZYNQ FPGA device you have to decide which of the PS peripherals you want to support in the hardware using the PS-MIO pins. You can also connect unused PS peripherals to the PL. For instance, most FPGA boards connect one PS UART to a connector on the board. You can also implement a UART in the PL that connects directly to the second unused PS UART using PL GPIO pins. The same is true for the Ethernet PHY interface. Of course your board also needs to have connectors that support the interface. A few PMODs would be fine for lots of UART interfaces without hardware flow control but you'd need an FMC or HSMC connector for an external Ethernet PHY. It doesn't work the other way; that is you can't connect an Ethernet PHY wired to the PS-MIO pins and connect it to your own custom MAC directly. In general the typical ZYNQ FPGA board doesn't directly support all of the PS peripherals in the device due to a lack of available MIO pins.

[zygot]

8 minutes ago, mikewu4466 said:

it seems possible to move data between the PS to PL

I suggest that you familiarize yourself with UG585 if you are using a ZYNQ-7xxx device. This will answer a lot of your questions.  Again, avail yourself of the wealth of information that Xilinx publishes about it's products.

One very easy way to pass data between the PS and PL is to use the AXI BRAM controller with a dual-clock BRAM making one side external to the block diagram. That you your HDL doesn't have to worry about AXI complexities. The HDL can just write formatted data samples and the PS can read them. I've done this many times.

It's really not clear what exactly you are trying to do. I'd do the easiest thing that supports the data rate/processing interval requirements for you project. Since you are thinking about UARTs this suggest a fairly low processing burden on your design. Since you have a nice processor with floating point this might be the place to processes data. It would certainly be easy to implement as many UART interfaces in your PL as you need.

[Clyde]

You are losing me in your problem description without a block diagram.  I too want to know how to go from the PS to PL and I think the answer lies in UG585.  My guess is it involves using the MIO not as a means to access peripherals, but just a general interface.  

It is curious that when configuring the ZYNQ, one can completely disable all of the peripherals.  

There are lots of things to learn.

Clyde

[mikewu4466]

Hey Clyde,

Thanks for the response. From some cursory searches online, it seems possible to move data between the PS to PL?

I ask because my application would like to sampling data through 3 ADC measurements while receiving data from 3 external sources via UART. There's a lot of processing going on, so I thought it would be best if I could create three modules in the PL to basically process a set of ADC data and UART data per module to parallelize the computation rather than computing everything serially in the PS.

I'm slowly starting to get a better grasp of interacting with the XADC in the PL, but it seems like the only feasible way of getting the UART data into the PL would be to move it from the PS somehow.

[Clyde]

UG585 talks of a serial interface for JTAG... but this seems like a very difficult way to go.

Writing HDL to access the XADC in parallel is well described in UG480.  Configuring the block in the IP configurator makes the HDL to drive it very simple.  The HDL example in UG480 is far more complicated than it needs to be, as the IP block can be completely configured in the IP configurator.

I had a simple example of the parallel mode, but I broke it.  Perhaps I will dust it off and fix it.

Clyde

 

[mikewu4466]

My goal is to basically implement an RX-only UART to receive data and process it within the PL. Or maybe there's a way to get the data from the PS after I've received it via AXI UART Lite and send it to the PL? I've already received the data through software written in the Xilinx SDK and that's working fine. It's possible that my question doesn't make much sense, I'm a little new to FPGA programming (trying to pick up where a colleague of mine left off on the project).

Do you know if projects like this exist? I'll also take a look around the forums.

[zygot]

5 minutes ago, mikewu4466 said:

As a quick aside, do you also know if documentation exists on using UART purely in programmable logic?

I'm not sure what you are referring to with you use of UART. It's certainly possible to implement a UART in logic using the HDL of your choice. If you are referring to a PS UART in a ZYNQ device that's another matter though you can implement an HDL UART in the PL and connect it to one of the PS UARTs. There a a number of complete and  TX only UART designs available in the Project Vault section of this Web Site. You can do a search for UART postings in the various sections as well.

[mikewu4466]

8 minutes ago, zygot said:

Use the Xilinx Document Navigator tool. There is an App. Note, with  accompanying Verilog project source,  about using the DRP with the XADC module though I don't remember which one it is. Always start with Xilinx documentation to understand what the various components in your FPGA are and how to design with them. There's a User Guide for the XADC and a very useful guide for instantiating primitives in VHDL and Verilog.

Thanks for pointing me to those resources, I'll take a look.

As a quick aside, do you also know if documentation exists on using UART purely in programmable logic? I've gotten UART working with the Xilinx SDK and the SoC, but I was wondering if it was possible to do reads from the UART RX FIFO buffer in Verilog. I've asked the question on the Xilinx forum but haven't gotten any replies so far.

[zygot]

3 hours ago, mikewu4466 said:

What tips do you have for getting started?

Use the Xilinx Document Navigator tool. There is an App. Note, with  accompanying Verilog project source,  about using the DRP with the XADC module though I don't remember which one it is. Always start with Xilinx documentation to understand what the various components in your FPGA are and how to design with them. There's a User Guide for the XADC and a very useful guide for instantiating primitives in VHDL and Verilog.

[zygot]

18 minutes ago, Clyde said:

I have some reading to do for sure.

Yes you do.

[Clyde]

Yes, it is a Zynq platform... I do assume you have the AXI-lite bus hooked up ;<}

I wired stuff up thinking I needed to before I saw the code examples.  I have some reading to do for sure.

Thanks again.

 

Clyde

[zygot]

I don't have anything "hooked up".

Let's back up a bit. You didn't mention what platform you are using. When someone mentions bare-metal I assume ZYNQ-based platforms.

The example applications provided by the SDK aren't intended to be solutions to projects, just tutorials. You have to read through them and understand what each project does and how it does it. Some driver examples do assume that you have hardware connections, like those assuming a loopback path, but generally they are self-sufficient. That doesn't mean that they do what you want to do.

For the xadcps polled example it just reads and prints internal a few rail voltages. If you want to read the ADC level on one or more of the analog input channels you have a couple of choices. One is to hunt around for a post of source code coding something close to what you want to do. Two is to read through the literature and figure it out for yourself. I recommend choice two. There are a number of ways to run the xadc hardware. 

[Clyde]

Somehow my first reply to the above got lost.  I see it now, and thank you.  I dismissed the  mss page examples because my simple attempt of reading the buttons and driving the LEDs was thwarted because the example code did not show how to read the buttons.  I am beyond that now.

Could you please post how you hooked up the XADC?   have CONVST coming out of a GPIO port and EOC going in, which seems reasonable to me.

Clyde

[zygot]

You open them in the SDK text editor. The system.mss will show all of the standalone drivers and point to documentation ( sometimes useful ) and example code that demonstrates how to use those drivers ( very useful ). Just select the example code projects that you want ot learn from and import it.. the SDK will automatically build it ( most often ) and you can then run it on hardware.

27 minutes ago, Clyde said:

All I have right how is a 7 segment display and one channel at a time.

You also have at least a PS UART. There are some nice example SDK code projects for using that peripherals as well. Note that it's possible to forgo the drivers and just create applications in C as well, or poorly, as you'd do with a regular uController. Dont be afraid to take some time and explore the tools. Sometimes just messing around is more productive than trying to do actual 'work'

 

[Clyde]

All of the system.mss files I have on my system are 5k bytes or smaller, so I don't quite get what to do with them.  I don't have any project that has anything like your "ps7_xacd_0 xacd_ps xadcps_polleded_printf_example.c" in it, so I am lost finding anything similar.

What I mean by kicking it up a notch is is to do some real world measurements, scale format the numbers and print them with printf.  All I have right how is a 7 segment display and one channel at a time.

Perhaps you could kindly point me a little closer?

Clyde

[zygot]

14 hours ago, Clyde said:

I did not find much of anything with system.mss.

Not sure what "much of anything" entails. When I opened my last ZYNQ project SDK I imported the ps7_xacd_0 xacd_ps xadcps_polleded_printf_example.c. What's missing for your needs? The Xilinx Document Navigator has a number of user guides, including ug480 that might help.

Maybe it's me but I find the comment about "kicking it up a notch" by doing in C what you've already done in an HDL mystifying. Guess that I've been doing both for far too long....

[Clyde]

Hi,

I did not find much of anything with system.mss.  I am well familiar with using the DRP and HDL to access the XADC, now I am just trying to kick it up a notch an do it in C.

Perhaps there is something I have missed.

Clyde

[zygot]

Open the system.mss file in the SDK for Vivado 2019.1 or earlier. There you will find a number of example project code examples for your design. Take the time to do some exploring in your tools, you might be enlightened.

BTW you can access the XADC through the DRP in all HDL designs and it it highly recommended for any serious Series7 designs for keeping track of substrate temperature if nothing else.

I haven't used Vitas to any extent using Vivado 2019.2 so I can't comment on how this works in that framework.