ZMod AXI_Zmod_DAC1411

[svaughn442]

Hi ,

I have purchased the Eclypse Z7 with ADC and DAC. I have started building the block design. I have downloaded the DAC1411 *.vhd files from GitHub. I can create an IP using the Create and Package IP tool. Is there a simpler way other than modifying the VHDL code to create an RTL module that I can add and connect to my block design?

thanks!

Stan

[zygot]

21 hours ago, svaughn442 said:

Is there a simpler way other than modifying the VHDL code to create an RTL module that I can add and connect to my block design?

Well, this depends on what you want to do. I'm assuming that you are eschewing the Digilent AXI IP and wanting to use the Digilent controller IP files as a template. From a functional viewpoint it's not clear to me what you want to change.

[svaughn442]

Well, I have a block diagram for the Zynq and I would like to use the Digilent Axi IP.   Our concept involves using DMA to update the DAC output to burst out Gaussian waveforms of several microsecond duration. I would like to connect the DAC interface to a DMA controller , but as IP blocks instantiated in the Block diagram canvas. I can create an AXI IP core and match the VHDL code from your ZMOD library and make this all play , but I would prefer to just have an IP  that I can connect up in the block design 

thanks

Stan

[zygot]

@svaughn442,

First let me make it clear that I don't work for or represent Digilent; I'm just a frequent customer. I also have the same kit as you do.

I suggest that before you do anything you rebuild the bare-metal and Linux demos for the ZMODs. You might be one of the fortunate few in finding that their current AXI IP is sufficient for what you want to do; that's for you to decide. I guess it would depend on your PRI. There's more to the story than block diagram IP blocks. You need to understand Digilent's IP delivery system for Eclypse-Z7.

My hunch is that (almost) everyone using the Eclypse-Z7 will want to create their own AXI substructure using the combination of available SYZYGY pods for their application. I haven't tried verifying compatibility with Eclypse-Z7 support and pods from other vendors yet. My sense is that anyone would be awfully lucky to find a simple way to connect the ZMODs to suit most applications. I don't see any value in doing all of the work of creating and packaging you own AXI IP block; just figure out what's available and appropriate for your needs and create the appropriate block diagram.

My personal preference is to create the minimal ZYNQ/AXI system necessary and instantiate the whole thing in a higher level HDL source. Even then I can be guaranteed that  Xilinx will break the design within a release or so.