Problem with Vivado Bitstream generation

[Delta_VII]

Hi, I am doing my first steps into VHDL, but I am struggeling. When I want to generate the bitstream of my design, I get this error:

Finished Running Vector-less Activity Propagation
INFO: [Common 17-206] Exiting Vivado at Tue Apr 26 23:19:35 2016...

*** Running vivado
    with args -log LED.vdi -applog -m64 -messageDb vivado.pb -mode batch -source LED.tcl -notrace


****** Vivado v2016.1 (64-bit)
  **** SW Build 1538259 on Fri Apr  8 15:45:27 MDT 2016
  **** IP Build 1537824 on Fri Apr  8 04:28:57 MDT 2016
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source LED.tcl -notrace
Command: open_checkpoint LED_routed.dcp

Starting open_checkpoint Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 206.754 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 8 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2016.1
INFO: [Device 21-403] Loading part xc7a35ticsg324-1L
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Users/kaipe/FPGA Projekte/LEDs/LEDs.runs/impl_1/.Xil/Vivado-32-KaiPC/dcp/LED.xdc]
Finished Parsing XDC File [C:/Users/kaipe/FPGA Projekte/LEDs/LEDs.runs/impl_1/.Xil/Vivado-32-KaiPC/dcp/LED.xdc]
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 427.617 ; gain = 0.000
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 427.617 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Project 1-604] Checkpoint was created with Vivado v2016.1 (64-bit) build 1538259
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti'
Running DRC as a precondition to command write_bitstream
INFO: [DRC 23-27] Running DRC with 2 threads
ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 1 out of 5 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: CLK.
WARNING: [DRC 23-20] Rule violation (CFGBVS-1) Missing CFGBVS and CONFIG_VOLTAGE Design Properties - Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
INFO: [Vivado 12-3199] DRC finished with 1 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.

INFO: [Common 17-206] Exiting Vivado at Tue Apr 26 23:20:32 2016...

My VHDL code is here:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity LED is
    Port ( CLK : in STD_LOGIC;
           led : out STD_LOGIC_VECTOR (3 downto 0));
end LED;

architecture Behavioral of LED is

signal count : integer range 0 to 99999999 :=0;
signal pulse: STD_LOGIC := '0';

begin

counter : process(CLK)
begin
if rising_edge(CLK) then
    if count = 99999999 then
       count <= 0;
       pulse <= not pulse;
       else
       count <= count + 1;
       end if;
    end if;
end process;

LED (3 downto 0) <= (others => pulse);

end Behavioral;

 

I hope you can help me.
Regards, Delta_VII

[hamster]

Hi! The problem is this:

 

ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 1 out of 5 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: CLK.

You have not defined which pin the CLK signal is being supplied on. If you add that to your .constraints ("xdc") file you should have more luck.

Mike

[Delta_VII]

Thanks, now it works