FPGA Ethernet without DDR Memory

[Jay D]

Greetings!

I am working on a personal project that involves Ethernet communications (10Mb) between a computer and a FPGA. I have seen the Ethernet design example using the Arty FPGA board. I am curious to know if anyone has implement a FPGA Ethernet Core that doesn't require external Memory? If you have, can you help me know how you did it.

Thanks,

Jay

[zygot]

@Jay D

Well this project might help get you started.

https://forum.digilentinc.com/topic/3968-ethernet-udp-echo-server/

I don't use 10/100 Ethernet much so I don't have anything to offer. If you are restricted to 10 Mbps Ethernet you might just want to use a UART over  USB. The interface is easier to understand and there's a lot less overhead so if you do a 10 Mbaud UART you will actually have better throughput and less latency. Also you don't need to support a lot of packet types. Also, you aren't bound to OS drivers and all of the "undesirable features" and security issues that come with a full TCP/IP stack. If you need all of that then I guess that you have to put up with the extras. A 10 Mbaud UART over USB will require some attention to detail for the OS application and likely hardware flow control with buffering on the FPGA side to compensate for when the OS is off doing things other than your application. I've found that anything above 921600 baud can be problematic.

If you are doing 100 Mbps Ethernet then USB 2.0 might be a reasonable alternative and competitive as far as data rates go.

My best advice is to understand the Ethernet PHY as a stand-alone data interface and learn how to transfer data, anything starting off with a preamble and SDF, between two PHYs. This could involve two PMODs with 10/100 Ethernet PHYs. You don't need a MAC or a soft-processor to do raw data communication over Ethernet between a PC and an FPGA board.

I'd expect that any approach you take will easier at the driver/application level on Linux. There's a reason why Microsoft doesn't use the catchphrase "have it your way" in their advertising. If their advertising were honest it would include the phrase " We are Microsoft. You will be assimilated" in all of its ad campaigns.

[D@n]

@Jay D,

Yes, I've implemented an Ethernet core for both the 100M on the Arty and the 1G Ethernet on the NexysVideo.  Neither of the two cores uses DDR memory for the ethernet, although they do depend upon block RAM.

As written, it's a touch difficult to get high throughput through them since the current mode of operation is to receive a packet, and then manually remove it from the network memory to do ... whatever with it.  Once removed from network memory, the network core is ready to accept the next packet.  When I get a chance to update the project, my plan is to add a packet length FIFO, and to double the RAM used so that more than one packet can be processed at a time.  Check out the comments in this file for more information on the low level driver.

Be aware that full protocol support takes some work.  Worse, without ARP and ICMP protocol support you may struggle to get the UDP or TCP support you want.  I accomplished this support through software for the ZipCPU.  Be aware that, without DDR SDRAM, your microcontroller performance will be limited either by running directly from flash or from using whatever's left of your block RAM.  As always, everything's a trade off.

Dan

[Jay D]

Zygot and Dan,

Thank you for commenting and providing me great information!

A little more information of my project. 10/100 Mbps Ethernet is all I need. I like the high temperature capability of a FPGA but adding external DDR memory reduces that capability (80C). The idea was to code a FPGA to have a few I2C buses and Ethernet interface. The I2C would be used to talk with a few temp sensors. The FPGA would package the data and send it out to a Ethernet PHY. I don't need to really send commands to the FPGA. On power up, I just need it to connect and stream data. I am sure easier said than done!   

I think I am going to try the Arty board and see if I can get something like this to work. 

Dan - Were you using a RTOS in your design?

Regards,

Jay

[zygot]

@Jay D

There are other projects in the Project Vault section that do what you want to do, at least the Ethernet transmit part. Creating simple packets is not difficult. You certainly don't need MicroBlaze, and RTOS, or any of that. This is a great all HDL project.

Just take the time to read the source here:

https://forum.digilentinc.com/topic/1985-arty-sending-udp-packets-without-any-software/

Not too difficult is it. If your PC OS is Linux you can write an application to capture the packets without a lot of hassle.

If you intend to put a switch between your FPGA server and PC you will need to create ARP advertising and response packets. This is almost trivial. If there's only a cable between the FPGA board and PC you just need to capture and parse the incoming packets; as long as your OS doesn't interfere. Getting the CRC and packet size is important.

[PhDev]

@Jay D

I recommend you to have a look at this tutorial. This core do all Ethernet protocols (ARP, DHCP, UDP, TCP, ICMP etc) that you need without use of any operating system or extra memory.

I use it all the time and have not found any problems. You can download and use it for free. The remote programmer also works great.

If you do any signal processing like I do there is also a remote logic analyzer that works very good as an internal oscilloscope.

[Jay D]

Zygot and Dan,

Thank you again for you comments and suggestions. I will check them out and I think I'll purchase an Arty A7 in the near future.

I do have a DECA Altera Max 10 demo board from Arrow that is not being used. Have you ever made an Ethernet core or done anything similar for that board?

Regards,

Jay

[zygot]

@Jay D

If you trust anything that I tell you trust me that you want to do your Ethernet experimentation in the Xilinx universe. Intel (Altera) has consistently made Ethernet development as difficult as they possibly can. I bought the nifty MAX10 Development and gave up on it for almost a year after trying to do 1G Ethernet with it. I've done a lot of no-MAC, no-processor 1GbE for years using Digilent and a handful of Xilinx boards. It wasn't until I realized that Quartus was "cheating" with the MAX10 demo code that I gave up trying to use the device according to the device documentation and official Quartus device support IP and made a breakthrough. I've since added the Cyclone V GT and MAX10 to my list of "Eth PHY as data pipe" clients. My only worry currently is that Digilent has seemed to have abandoned FPGA development in favor of  ZYNQ dependent platforms. SIGH!!!! 

If you want a taste of what you can do with a good ol' 1GbE PHY check out this post:

https://forum.digilentinc.com/topic/17006-resolving-chronic-itch-with-the-ethernet-phy/

I'm in the middle of revising an older 1GbE Ethernet Test tool that was submitted to the Project Vault a while ago. It uses the MAX10 Development Kit and a FT601 USB 3.0 bridge on the HSMC connector. I've managed to get both PHYs working as DUTs with a version of the test tool in the Project Vault. Arranging the PHYs as one pass-through 1GbE connection has proven to be challenging, even though I know that the RTL is fine. There was a time when Quartus was a great tool compared to what Xilinx has to offer but not these days; especially if you don't have $6-7K for annual subscriptions. I could be wrong but my sense is that Quartus is now a tool designed to encourage customers to spend money in a higher tier market.... Oh, the games that companies play...

[D@n]

@Jay D,

No, I haven't done Ethernet work on any Intel chips.  I have done some work on an ECP5 Versa board, however.  Indeed, I like the software from that board better.  Moreover, even though the ECP5 Versa board has DDR3 SDRAM memory, the design never used any--so it might be a useful example to you.  Thankfully, the differences between the Nexys Video (GbE) and the ECP5 Versa (GbE) board were very minimal.

Dan

[zygot]

Just a note. There are some fundamental differences between 10/100 and 1GbE PHYs. There are fundamental differences between 10GbE PHYs and everything else. Yes, there are PHYs for 10GbE over copper. I've only read about 1 FPGA board with 10GbE that's affordable but I have no idea if it's real. If you get the ARTY A7 you are getting 10/100. There's nothing wrong with that except the throughput; but timing is a whole lot easier.

[Jay D]

Zygot,

What you have said is my experience too. With the help of Google I ended up at this website. I didn't find anyone in the other universe that has done what you and Dan have with a Ethernet interface.

This has really sparked my interest in getting an Arty A-7 demo board in and playing. 

Regards,

Jay

[Jay D]

Thanks Dan!

Zygot, All I need is 10/100 and I am fine!

[xc6lx45]

Hi,

I'd have a look at sending timestamped UDP packets, as opposed to TCP/IP. It avoids most of the complexity, and may be closer to the physical reality (e.g. there is no point in buffering new outbound data to wait for retransmission of a lost packet that will then be stale and irrelevant when it eventually arrives.

 

[zygot]

14 hours ago, xc6lx45 said:

I'd have a look at sending timestamped UDP packets, as opposed to TCP/IP.

Good advice, but if all you are doing is connecting two devices you don't need to support most of Ethernet's capabilities or even standard packet types.

The first thing that you need to do is establish that your PHY interface is rock solid. After that there are choices and trade-offs to consider. My advice is to be prepared to experiment and learn. For a limited number of targets there might well be plug in solutions but taking the time to figure it all out for yourself is worth it.