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Vivado 18.2 crashes in tutorial after creating Verilog source file


jpotter0

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I just got a Cora Z7-10 board. I'm tryin to follow the tutorial "Getting Started with Vivado." According to the information I saw I am supposed to be using Vivado 18.2. I have it installed as well as 18.3 and 19.1. I start out following the instructions, which seem very clear. Everything goes as expected through adding the constraints. The next step is to create a Verilog source file. I follow the directions through finish. Then the define Module window appears. I set clk as an input and led as an output, after previously editingĀ  the constraints file. After I click on OK and in a second or so the window disappears and Vivado shuts down. This has repeated 3 times, each time I am carefully following the instructions in the tutorial. What gives?

Thanks - Jim

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Success! The LED is blinking. Now I can get on to learning how to do something with it. My initial goal is to make an 8 bit time base with the master clock rate adjustable 1 pps to 1000 pps by Ethernet command, and with each bit having an Ethernet programmable delay and pulse width with a resolution of 0.1 ns or better. If there is already a canned package that can do something like this or be modified to do it, I'd greatly appreciate any pointers. It's now past 3 AM, about the end of my evening. I will pursue this further in the morning. It turns out to have been a good choice to start with the Cora Z7. I tried the Trenz TE0723 and theTE0720 with the TE0705 test board. I could not make it through the tutorial without some kind of problem. It the tutorials are confusing or I'm easily confused. The Digilent tutorial is clear at every step. My only problem was being directed to Vivado 18.2 when 18.3 appears to work fine. - Jim

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3 hours ago, jpotter0 said:

My only problem was being directed to Vivado 18.2 when 18.3 appears to work fine

I'd say that the problem is that any version of Vivado 18.x doesn't work on the first try. This shouldn't and doesn't have to be so hard.

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