newkid_old Posted October 21, 2019 Share Posted October 21, 2019 I'm wondering if there's a way to modify the Arty Echo Server example project to utilize BRAM on the FPGA vice the DDR chip on the board? Thanks in advance. Link to comment Share on other sites More sharing options...
Ana-Maria Balas Posted October 25, 2019 Share Posted October 25, 2019 Hello @newkid_old, Which Arty do you want to use ? Ana-Maria Link to comment Share on other sites More sharing options...
newkid_old Posted October 26, 2019 Author Share Posted October 26, 2019 I have the the Arty A7-35. Link to comment Share on other sites More sharing options...
Ana-Maria Balas Posted October 29, 2019 Share Posted October 29, 2019 On 10/26/2019 at 8:11 PM, newkid_old said: I have the the Arty A7-35. I can say that Arty A7-35 has a small BRAM for this project and the only way is to store the application in DDR. I had at hand an Echo Server example project and I verified the size of the elf and it's approximately 283 KB, and the Arty A7-35 has only 225 KB of BRAM. Even if you somehow minimize the size of the elf, I still don't think you can fit it in BRAM. Cheers, Ana-Maria Link to comment Share on other sites More sharing options...
newkid_old Posted October 29, 2019 Author Share Posted October 29, 2019 Thanks for you reply. Do you think the Arty a7-100 could handle the task? Link to comment Share on other sites More sharing options...
Ana-Maria Balas Posted October 30, 2019 Share Posted October 30, 2019 11 hours ago, newkid_old said: Thanks for you reply. Do you think the Arty a7-100 could handle the task? I looked more into this issue and I was wrong because not the physical size of the elf file matters, but the sections sizes of the elf. As you can see below the bss section takes up to ~3.8 megabytes of BRAM space. The Arty A7 100 have around 600 KB of BRAM memory. The LwIP is too large to fit in BRAM. The only solution is to use DDR. https://forums.xilinx.com/t5/Processor-System-Design/error-section-bss-will-not-fit-in-region/td-p/885788 Link to comment Share on other sites More sharing options...
newkid_old Posted October 30, 2019 Author Share Posted October 30, 2019 Thank you for help on this. Link to comment Share on other sites More sharing options...
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newkid_old
I'm wondering if there's a way to modify the Arty Echo Server example project to utilize BRAM on the FPGA vice the DDR chip on the board?
Thanks in advance.
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