I am new using FPGAs, so I assume this question may be easy, but I have been trying several demos and forums and I cannot find the anwer to my problem.
I am using an Arty S7
My objetive was to use the XADC wizard to process and analog signal and pass it through the uart to the terminal. I would like to do this using the microblaze. The error I obtain is the following:
[DRC UCIO-1] Unconstrained Logical Port: 5 out of 23 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: channel_out_0[4:0].
Which makes sense because, as it can be seen in the image, the output of the XADC wizard is not connected to anything.
How could I connect this properly? Thank you very much:)
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Nacho Lopez
Hello,
I am new using FPGAs, so I assume this question may be easy, but I have been trying several demos and forums and I cannot find the anwer to my problem.
I am using an Arty S7
My objetive was to use the XADC wizard to process and analog signal and pass it through the uart to the terminal. I would like to do this using the microblaze. The error I obtain is the following:
[DRC UCIO-1] Unconstrained Logical Port: 5 out of 23 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: channel_out_0[4:0].
Which makes sense because, as it can be seen in the image, the output of the XADC wizard is not connected to anything.
How could I connect this properly? Thank you very much:)
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