I'm trying to use the "cat file.bin > /def/xdevcfg" technique to load an FPGA bitstream into the Zynq on my Cora-Z7-10 board from Linux but it hasn't worked; every time I try it I get "cat: write error: Connection timed out". Does anyone know whether this is a known issue or what?
I've tried the cora_z7_10_wrapper.bit directly, then the same file but re-generated from the Cora Vivado project (checking that the content is binary identical), then modified the settings so that the bit file is not compressed and also generates a bin file, and tried both of those (as well as the bin file with the bytes revered in groups of 4). All the same result.
Also, I noticed mention somewhere of checking /proc/interrupts and seeing if interrupt 40 gets updated after the cat; it does, so something's getting in there, but....
Have you any other ideas on things I could try?
John
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jmccabe
Hi
I'm trying to use the "cat file.bin > /def/xdevcfg" technique to load an FPGA bitstream into the Zynq on my Cora-Z7-10 board from Linux but it hasn't worked; every time I try it I get "cat: write error: Connection timed out". Does anyone know whether this is a known issue or what?
I've tried the cora_z7_10_wrapper.bit directly, then the same file but re-generated from the Cora Vivado project (checking that the content is binary identical), then modified the settings so that the bit file is not compressed and also generates a bin file, and tried both of those (as well as the bin file with the bytes revered in groups of 4). All the same result.
Also, I noticed mention somewhere of checking /proc/interrupts and seeing if interrupt 40 gets updated after the cat; it does, so something's getting in there, but....
Have you any other ideas on things I could try?
John
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