register clear on raed

[kamal]

hi all !

I am doing a BER (BIT ERROR RATE) in vhdl and I have to put 2 registers clear on read which counts the number of words in error and the number of bits in error. i want to know what is a register clear on raed and how i can code a register clear on read in vhdl?

thank you,

[OvidiuD]

Hello, kamal!

Basically you have to make the register have only 0's when you give it a signal. I'd say something like this:

begin

     if rising_edge(CLOCK) then

             if ClearTheRegister = '1' then

                    MyRegister<= ( others => '0');

              elsif WriteInRegister = '1' then

                    MyRegister <= SomeNewData;

              end if;

       end if;

end process;

Best regards, Ovidiu

[xc6lx45]

The idea is also known as "read-sensitive".

One thought: Most likely, you want to know both numbers at one common point in time. Unless you stop the test, the two reads are not atomic, and register contents may change between them.
One possible solution is to agree between RTL and driver SW that register A (e.g. "number of words") is read first, then register B (e.g. "number of bits").
The RTL code would then, on a read event on register A, return contents of A on the bus and at the same clock cycle copy contents of B into a "shadow register", say C.
The driver software first reads from A, then slightly later from C. No matter the time interval between the reads, the two numbers are guaranteed to be consistent.

Background info: This pattern is frequently found with combination with time stamps: Say, we need to know the "hardware time" T and a number of readings Q, R, S, ... exactly at that time.
So I define one read-sensitive register for T that returns the time stamp and at the same time copies Q, R, S to shadow registers that can be read through the bus.

Register sensitivity is a wonderful feature to dramatically reduce SW driver complexity in RTL design (and, like most things clever, can backfire horribly if you outsmart yourself or your colleagues).