Hi @m72 This may look like a digital issue, from ADC to FPGA... but i don't it is since we should see similar glitch on the upper side too. Could you provide detail about the experiment? I see you have set 10x probe... Are you using (single ended) BNC probe at 10x ? In case you are using differential input with high common mode voltage, the signal might enter in limitation or clamping starts to act, which also depends on the offset: https://reference.digilentinc.com/reference/in