OpenCL and emulator for FPGA accelerator

[rompish]

Hi Everyone,

I am a pretty seasoned C++ programmer dealing with low level things but I am brand new to FPGA topic.

I have read some articles, watched a dozen or two videos and looked into some boards and I would like to start my first project but dont know where to start. I have a few questions:

1. Do i need to learn Verilog/VHDL if i plan on using openCL? 

2. Do all boards "support" openCL? 

3. Do i need to actually buy a board to start working on my project or i can just use a Software Emulator for one? If i can use an Emulator, where do i get it?

4. Could you suggest any openCL starting guides and tutorials that are easy to understand for someone who doesn't know Verilog/VHDL or FPGA in general?

My project goal is to have a "smart" network interface that would pre-process data arriving on Ethernet and store it on host machine RAM directly, so that my C++ program running on CPU can use that data.

Thank you!

[xc6lx45]

I have used openCl only on GPUs but the first search turned up a link with this:

>> Specifically, we use Intel FPGA SDK for OpenCL that allows modern Intel FPGAs to be programmed as an accelerator, similar to GPUs

I suspect this architecture may not mix too well with network data processing: The architectural paradigm on GPUs is "one control path, many data paths" but I think you will need many parallel, independent control paths. GPUs win by massive parallelism / memory bandwidth via bitwidth. The clock speed is fairly low (=> higher end-to-end latency). Just like on FPGAs.

You may be able to find a simple example on the web looking for the following functions: clCreateProgramWithSource clBuildProgram clCreateKernel clSetKernelArg. In principle, a complete example can fit into one screen length but some "simple" things like take the maximum of a vector (reduction operations) turn out to be not simple at all...

If anybody has experience with openCl specifically on FPGAs, please feel free to correct me...

 

[xc6lx45]

you might have a look at the HLS (high level synthesis) toolkit. Pay attention to tool license issues / cost.

[zygot]

On 5/25/2019 at 5:53 AM, rompish said:

I am a pretty seasoned C++ programmer dealing with low level things but I am brand new to FPGA

Welcome to a new world. My personal opinion is that your software background will, in the long run, be an obstacle to getting proficient with FPGA development. FPGA vendors would like you to believe that you can use their tools and create any kind of project that you want without having to learn the details about logic design and modern programmable logic tool design flows. To an extent, as long as you are content to view painting in coloring books as art it is possible to believe that this is correct. In the long run though you will find that there is a lot of conceptual challenges and re-learning to do in order to be able to create personal expressions of FPGA art that accomplishes meaningful objectives. So I'm in the camp that will advise you to learn an HDL like Verilog or VHDL, preferably in a formal or quazi-formal way to start. There are other approaches like System C but I'd recommend those for people already expert in one of the tow previously mentioned. My background is hardware design branching into software with a few decades of FPGA development. I mention this because it's easy to confuse software development concepts as the same as  FPGA development concepts and this will be a problem. Not everyone will agree with me on this but my opinion is not just speculation.

As  for Open CL this is one of those 'platforms' that tries to make integrating FPGA development into software development a seamless experience. Again I don't believe that such an animal exists. As has been pointed out in the previous post be aware of the costs for using Open CL. As far as I know you will need to buy a licence to use Open CL with Xilinx tools. Intel will extract a significant annual  subscription fee to even develop with all but the older low end devices and in general tools like MATLAB integration or Open CL cost extra. Xilinx is willing to sell you a node-locked license to work with a specific device supporting a particular board, and that license is permanent as long as it is used with a particular version of the tools. Intel is not that generous and you might even find yourself having to purchase more than one version of Quartus to develop for two different device families. There was a time when Altera would sell you a USB dongle that allowed using a licensed version of Quartus one any machine in perpetuity but this is no longer the case. As a rule Xilinx and most other FPGA vendors will allow anyone to work with any device without spending $3000/yr on tool licenses but Intel will not. Intel is just more selective about potential customer relationships in terms of financial resources. A generally universal rule of technology is that you pay for convenience or simplicity and the cost (money being the least problematic part of the cost) is usually higher in the long run than you would initially ever agree to.

In FPGA logic we use a logic simulator to test logic designs, not emulators,  and they support Verilog or VHDL very well ( Verilog better than VHDL because Verilog has better support for simulating heirarchal designs than VHDL ). You needn't, I'd argue shouldn't, need hardware to get started with FPGA development; just the free version of Vivado or Quartus or whatever other vendor tool is required. Be aware that simulation is in itself a skill requiring some expertise in an HDL and logic design. I personally do, and advise everyone else, to try building a project, to the extent possible, using the available tools and demo projects for a particular board before getting committed to it by spending a lot of money. By 'extent possible' I mean that if your board has a device not supported by the free version of the tools you will not be able to do much. At the least this means that you can't create a bitstream to configure a device ( you don't care because you don't have the hardware to configure anyway...) but often you can't even simulate or get through synthesis much less place and route for an unsupported device. 

The bottom line is that before spending money do your 'due diligence' in researching what you are getting yourself into.

On 5/25/2019 at 5:53 AM, rompish said:

My project goal is to have a "smart" network interface that would pre-process data arriving on Ethernet and store it on host machine RAM directly, so that my C++ program running on CPU can use that data.

You can do this without Open CL using a board with both a PCIe interface and Ethernet PHY and all Verilog or VHDL source code. I've done this using a Cyclone V GT board ( which happens to be supported by the free Quartus tools and is a very capable but not terribly expensive board ) as well as the KC705 board and a few others.. It is not a good project for a complete FPGA newbie. If you have more money than you know what to do with you can probably do this to satisfy your initial needs using Open CL or other platform without having to become skilled in an HDL or FPGA tool flow details but it isn't something that I'd want to try, knowing what I know about FPGA development. About the part where the FPGA stores data in the PC RAM... current FPGA devices will require a software driver to pass data through a PCIe or USB interface. Intel recently announced a new Agilex family  of devices with CXL that might someday allow just what you want to do... but I don't envision having the money to get past the bouncers guarding the door to the dance so that I can try it out for myself.

You can also do the same thing using a board with an Ethernet PHY and a USB 3.0 interface by the way and it could be fairly easy to do if your Ethernet traffic is mostly one way.

[Added thought]

Many year ago Altera announced that it was developing an optical interface as a alternative to those messy, costly, slow, limited IO pins. My second thought after "WOW! how cool is that?" was gee it won't be long before Altera gets bought out by the biggest, baddest ape in the jungle. It seems that the technical challenges to such a scheme were more than Altera could resolve but my second thought turned out to be prophetic, if somewhat inaccurate. I'm still hoping for that optical interface to show up one day.... a guy can dream can't he?