Dynamic voltage and frequency scaling

[Mukul]

Hi

Is it possible to implement DVFS technique on FPGA board (i have zybo zynq-7000).

[zygot]

22 hours ago, Mukul said:

Is it possible to implement DVFS technique on FPGA board

What exactly is it that you want to accomplish?

[Mukul]

Hello

I have a ZYBO zynq-7000 SoC/FPGA  board, is it possible to present DVFS on it.

Means can i reduce the power/voltage consumption and frequency of any design.

For now I now about clock wizard, DCM, PLL for different clock generation (frequency) but this is not frequency scaling mi right?

And i have no idea about power reduction other than optimization ( again, which is not a voltage scaling).

So my question is, how to achieve this voltage and frequency scaling in FPGA environment, is there any technique.

Anything which relate front-end VLSI with DVFS

Thanks for the support.

[xc6lx45]

>> is it possible to present DVFS on it.
>> For now I now about clock wizard, DCM, PLL for different clock generation (frequency) but this is not frequency scaling mi right?

you may have your own answer there. This is some university project?

Have you done your own research? For example, this has all the right keywords:
https://highlevel-synthesis.com/2017/04/12/voltage-scaling-on-xilinx-zynq

[xc6lx45]

https://www.xilinx.com/support/documentation/white_papers/wp389_Lowering_Power_at_28nm.pdf page 3

[kwilber]

Here are two additional articles I have read on the technique being applied to a zynq.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842065/Zynq-7000+AP+SoC+Low+Power+Techniques+part+5+-+Linux+Application+Control+of+Processing+System+-+Frequency+Scaling+More+Tech+Tip

https://github.com/tulipp-eu/tulipp-guidelines/wiki/Dynamic-voltage-and-frequency-scaling-(DVFS)-on-ZC702

 

[zygot]

20 hours ago, Mukul said:

Means can i reduce the power/voltage consumption and frequency of any design

Well, power consumption in an FPGA is related to clock rates and output pin toggling rates. So the lower your clock rate the lower the power consumption. Does that mean that your design can run at some arbitrarily low clock rate to achieve some minimum power dissipation? I don't know. It depends.

I do remember when there was an effort to commercialize clockless FPGA devices using delays for synchronization and skew management; didn't last long.

If low power consumption is the most important specification then there are FPGA families designed for those applications. Choosing the right device for a particular application is part of hardware design. Xilinx Series7 devices do support clock enables so that you can "power down' parts of a design when not needed similar to ASIC devices.

You can learn more about optimizing FPGA designs for a particular need by reading the vendors' reference manuals and user's guides for devices and tools. That would be your best option.

[edit] Your question is about dynamic voltage and frequency management. Having the capability to do something is one thing but being able to do it is quite another thing. As a purely intellectual exercise I suppose that trying to manage voltages could be interesting but you had better understand the specifications in the data sheet for your device before trying any ideas on hardware.