Jump to content

Serdes Communication

Recommended Posts


  I am trying to create a Serdes connection to a Zynq 7020 device operating at 1.08Ghz per lane with 16 lanes of data. I do not have much expertise in this area and would like some guidance on where I should look for assistance. Also I'm running a Zed Board and can attach and FMC device and if there is a 2 way communication hardware so that I can read and test the communications, that would be the best. Let me know what you think.

Thank You


Link to comment
Share on other sites


I suspect that your only option is the FMC connection. In theory, even the LPC FMC offers enough differential pins to do 16 channels of SERDES. Theory and practice are rarely the same in the FPGA development board sphere. You say that you don't have much expertise with SERDES. That will have to change. You must read the Xilinx Series 7 SelectIO and Clocking user's manuals. Understand what the various clock buffer options are and what the limitations for using them are. I assume that you intend to have a source synchronous interface and you must understand the limitations for clocking SERDES. I don't know of any FMC mezzanine cards that provide 16 channels of differential signalling plus clocks routed to the right pins for any FMC equipped FPGA board that I own ( and I have quite a few ). I have no idea if the Zedboard even routes the FMC signals as differential pairs. If you are prepared to design your own FMC mezzanine card you might be able to use the Zedboard FMC connector... you'll have to trace through the pin and IO Bank assignments to be sure.

If you have a low reference clock to SERDES bit rate ratio then IOSERDES isn't too complicated. If you want to do 14X-16X things get complicated.

Read through applicable application notes fro Xilinx such as XAPP524, XAPP585, XAPP595 etc for some insight as to what you are getting yourself into.

Unfortunately, having an FMC connector on a board is no guarantee that it will work for every application.. it depends on the PCB routing and pin assignments.

I would definitely start off with 1 channel TX and 1 channel RX in a loopback configuration as a starting point.

Do I understand correctly that you want to use the Zedboard as a data sink for a 16 channel SERDES interface? Knowing what the data source will be is necessary to make intelligent commentary about any specific implementation.

Opal Kelly has a couple of boards with Syzygy specification ports. The standard ports support 8 channels of differential pairs but you have to confirm that the differential and clock pins are all on the same IO bank. This might be the easiest way to create a few projects to learn about SERDES. Opal Kelly did a good job with Syzygy.

Trust me, you want to develop your skill starting with a simple project and building up to a higher performance design. Your goals are pretty demanding in terms of low end FPGA performance and complexity. How do you intend to process 2 GB/s of data? You will have to have some pretty wide busses somewhere in your design.

Link to comment
Share on other sites

Hi Zygot,

    Your explanations are spot on. We are taking in camera data across 16 "serdes" pairs operating @ 1.08Ghz. TThe camera is transmitting the clocking based from a clock produced from the FPGA @ 90 Mhz. The Camera is handling the workload, but the serdes is the collection system for the data. The data will be intensity checked when it arrives and placed into a buffer for analysis. Each frame will produce a subset of values that will transmitted out . So you can see only a part of the data will be kept and stored in memory, but a "ping pong" memory will be used to work the data out while another frame is collected. We will store frame output data and sream across an ethernet communication link. The data itself per pixel is 10 bit and at the most we will be storing 60000 words or 120000 bytes per frame before sample. Sample output for an entire frame is only 2400 bytes across ethernet.

I appreciate your assistance.

Link to comment
Share on other sites

We can build a 4 lane unit for testing, The camera may be placed in a test mode where the bits are flipped to produce alternating patterns to determine "Eye Center" by adding and subtracting delays. We plan to make our board pairs on the PCB an exact length with the clocking. We should not require much delay work.

Thank you


Link to comment
Share on other sites

2 hours ago, cucchi said:

We plan to make our board pairs on the PCB an exact length with the clocking.

Sounds like interesting project.

In addition to what I've already mentioned don't forget to verify that the FPGA platform FMC traces are suitably length matched for each differential pair. Also be sure that your IO banks have the correct Vcco to support the IOSTANDARD of your requirements. I'd also do an analysis of the FPGA platform power supply. It might be helpful to use one of the application note projects set up as close to your needs as possible as a test and see what Vivado guesses the power requirements are for this kind of application. FPGA development boards are not usually designed to handle bleeding edge applications. Since your data is being driven externally you should be OK but I'd want to have a warm feeling before trying to make hardware work.

Make sure that you understand cascaded ISERDES2 limitations for SDR and DDR data. Hopefully your camera can supply DDR LVDS data to avoid a cascaded ISERDES2 implementation. Unfortunately, there aren't many cascaded ISERDERS2 or OSERDES2 cascaded example projects to play with.

Don't plan on getting lucky... so extensive and solid prep work before committing to a PCB interface board  is essential. 

Link to comment
Share on other sites


This topic is now archived and is closed to further replies.

  • Create New...