fpga_babe Posted April 26, 2019 Share Posted April 26, 2019 Hi all, I am new to FPGA and it is my hobbies. Most of my job is to design RTL IP and ASIC related work. Currently, I am investigating bus interface in general from UART, I2C, PS-2 to AXI, SPI and so on. My target is to build an IP set to adapt the peripheral using those Interface. Hope to see someone in the same interest. Link to comment Share on other sites More sharing options...
Sduru Posted April 26, 2019 Share Posted April 26, 2019 I am also interested in this kind of task. But I will be using AXI Stream and MIPI interfaces with a lot errors that I need to solve.. Link to comment Share on other sites More sharing options...
fpga_babe Posted April 26, 2019 Author Share Posted April 26, 2019 54 minutes ago, Sduru said: I am also interested in this kind of task. But I will be using AXI Stream and MIPI interfaces with a lot errors that I need to solve.. Hi, thanks for a reply. Let share the project and problem. We can learn from them. Link to comment Share on other sites More sharing options...
zygot Posted April 26, 2019 Share Posted April 26, 2019 11 hours ago, fpga_babe said: I am new to FPGA Since you already have a strong HDL and logic foundation the only advice, based on experience with ASIC designers, that I can offer is to thoroughly immerse yourself in the documentation related to a particular FPGA device and the Xilinx toolset. Link to comment Share on other sites More sharing options...
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